EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 250

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

9–30
Table 9–8. Dedicated JTAG Pins (Part 2 of 2)
Figure 9–16. JTAG Configuration of a Single Device Using a Download Cable
Notes to
(1) Connect the pull-up resistors to the V
(2) Connect the pull-up resistor to the same supply voltage as the USB-Blaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster cable. Connect the
(3) Connect the nCONFIG and MSEL[3..0] pins to support a non-JTAG configuration scheme. If you only use the JTAG configuration, connect
(4) In the USB-Blaster, ByteBlaster II, and ByteBlasterMV cables, this pin is a no connect.
(5) You must connect nCE to GND or drive it low for successful JTAG configuration.
(6) Resistor value can vary from 1 K
Arria II GX Device Handbook, Volume 1
TMS
TCK
Name
Pin
voltage supply to the V
nCONFIG to V
Figure
9–16:
Test clock
Test mode
CCIO
select
Pin Type
input
, and MSEL[3..0] to GND. Pull DCLK either high or low, whichever is convenient on your board.
CCIO
V
During JTAG configuration, you can download data to the device on the PCB through
the USB-Blaster, ByteBlaster II, ByteBlasterMV, or EthernetBlaster download cable.
Figure 9–16
To configure a single device in a JTAG chain, the programming software places all
other devices in bypass mode. In bypass mode, devices pass programming data from
the TDI pin to the TDO pin through a single bypass register without being affected
internally. This scheme enables the programming software to program or verify the
target device. Configuration data driven into the device appears on the TDO pin one
clock cycle later.
CCIO
10
power supply of I/O bank 8C of the device.
(1)
kΩ
V

CCIO
GND
10
(3)
(3)
(3)
to 10 K
Input pin that provides the control signal to determine the transitions of the TAP controller
state machine. TMS is evaluated on the rising edge of TCK. Therefore, you must set up
TMS before the rising edge of TCK. Transitions in the state machine occur on the falling
edge of TCK after the signal is applied to TMS. If the JTAG interface is not required on the
board, you can disable the JTAG circuitry by connecting this pin to logic high.
Clock input to the BST circuitry. Some operations occur at the rising edge while others
occur at the falling edge. If the JTAG interface is not required on the board, you can
disable the JTAG circuitry by connecting this pin to GND.
kΩ
(1)
CCIO
N.C.
shows the JTAG configuration of a single Arria II GX device.
power supply of I/O bank 3C.

Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
.
nCE
nCE0
CONF_DONE
nCONFIG
MSEL[3..0]
DCLK
nSTATUS
Arria II GX Device
(5)
TDO
TMS
TCK
TDI
(6)
V
CCIO
V
(2)
CCIO
(2)
(6)
Description
1
kΩ
GND
Pin 1
10-Pin Male Header
Download Cable
(JTAG Mode)
(Top View)
GND
V
CCIO
V
IO
(2)
(4)
© July 2010 Altera Corporation
GND
JTAG Configuration