EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 32
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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2–6
Figure 2–6. Arria II GX ALM Connection Details
Arria II GX Device Handbook, Volume 1
datac0
datac1
dataf0
datae0
dataa
datab
datae1
dataf1
Figure 2–6
The clock and clear control signals of an ALM’s register can be driven by global
signals, general-purpose I/O pins, or any internal logic. General-purpose I/O pins or
internal logic can drive the clock enable. For combinational functions, the register is
bypassed and the output of the look-up table (LUT) drives directly to the outputs of
an ALM.
Each ALM has two sets of outputs that drive the local, row, and column routing
resources. The LUT, adder, or register output can drive these outputs (refer to
Figure
or direct link routing connections, and one of these ALM outputs can also drive local
interconnect resources. This allows the LUT or adder to drive one output while the
register drives another output.
3-INPUT
3-INPUT
3-INPUT
3-INPUT
4-INPUT
4-INPUT
2–6). For each set of output drivers, two ALM outputs can drive column, row,
LUT
LUT
LUT
LUT
LUT
LUT
shared_arith_out
shared_arith_in
shows a detailed view of all the connections in an ALM.
carry_in
carry_out
+
+
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices
V CC
GND
clk[2:0]
syncload
sclr
aclr[1:0]
reg_chain_in
© June 2009 Altera Corporation
D
D
CLR
CLR
reg_chain_out
Q
Q
Adaptive Logic Modules
local
interconnect
row, column
direct link routing
row, column
direct link routing
local
interconnect
row, column
direct link routing
row, column
direct link routing
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