EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 44
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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3–4
Figure 3–2. Arria II GX Byte-Enable Functional Waveform for MLAB
Packed Mode Support
Address Clock Enable Support
Arria II GX Device Handbook, Volume 1
current data: q (asynch)
contents at a1
contents at a0
contents at a2
address
byteena
inclock
wren
data
Figure 3–2
control the operations of the MLABs. The write operation in MLABs is triggered by
failing clock edges.
Arria II GX M9K blocks support packed mode. The packed mode feature packs two
independent single-port RAMs into one memory block. The Quartus II software
automatically implements the packed mode where appropriate by placing the
physical RAM block into true dual-port mode and using the MSB of the address to
distinguish between the two logical RAMs. The size of each independent single-port
RAM must not exceed half of the target block size.
All Arria II GX memory blocks support address clock enable, which holds the
previous address value for as long as the signal is enabled (addressstall = 1).
When you configure the memory blocks in dual-port mode, each port has its own
independent address clock enable. The default value for the address clock enable
signals is low (disabled).
XXXX
an
XX
doutn
FFFF
FFFF
shows how the write enable (wren) and byte-enable (byteena) signals
FFFF
a0
10
FFFF
ABFF
ABCD
FFFF
a1
01
FFCD
FFFF
a2
11
ABFF
ABCD
a0
Chapter 3: Memory Blocks in Arria II GX Devices
ABFF
FFCD
© November 2009 Altera Corporation
ABCD
a1
XXXX
XX
FFCD
a2
Memory Features
FFCD
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