EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 191

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
Differential Transmitter
Differential Transmitter
Figure 8–3. Arria II GX LVDS Transmitter Block Diagram
Notes to
(1) In SDR and DDR modes, the data width is 1 and 2, respectively.
(2) The tx_in port has a maximum data width of 10.
Serializer
© July 2010
Figure
Altera Corporation
8–3:
tx_coreclock
Fabric
FPGA
tx_in
The serializer takes parallel data up to 10-bits wide from the FPGA fabric and
converts the parallel data to serial data before sending the serial data to the
differential output buffer. The differential output buffer supports programmable
pre-emphasis and programmable voltage output differential (V
drive out mini-LVDS and RSDS signaling levels.
LVDS transmitter.
The serializer takes parallel data from the FPGA fabric, clocks it into the parallel load
registers, and serializes it using the shift registers before sending the data to the
differential output buffer. The MSB of the parallel data is transmitted first. The
parallel load and shift registers are clocked by the high-speed clock running at the
serial data rate (diffioclk) and controlled by the load enable signal
(LVDS_LOAD_EN) generated from the PLL. You can statically set the serialization
factor to ×4, ×6, ×7, ×8, or ×10 using the ALTLVDS megafunction. The load enable
signal is derived from the serialization factor setting.
You can bypass the serializer to support DDR (×2) and SDR (×1) operations to achieve
a serialization factor of 2 and 1, respectively. The I/O element (IOE) contains two data
output registers that can each operate in either DDR or SDR mode.
the serializer bypass path.
10
Center/Corner PLL
DIN
Serializer
3
DOUT
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
2
IOE
tx_inclock
(Note
1),
LVDS Transmitter
(2)
IOE supports SDR, DDR, or
Non-Registered Datapath
Figure 8–3
LVDS Clock Domain
Arria II GX Device Handbook, Volume 1
is a block diagram of the
OD
+
-
) controls, and can
Figure 8–4
tx_out
shows
8–7