EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 20
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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1–6
Table 1–4. Sample of Supported Protocols and Feature Descriptions
Arria II GX Device Handbook, Volume 1
PCIe
XAUI/HiGig/HiGig+
Gbe
CPRI/OBSAI
Supported Protocols
1
Table 1–4
for implementing these protocols.
For other protocols supported by Arria II GX devices, such as SONET/SDH, SDI,
SATA and SRIO, refer to the
The following sections provide an overview of the various features of the Arria II GX
FPGA.
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lists common protocols and the Arria II GX dedicated circuitry and features
Complete PCIe Gen1 protocol stack solution compliant to PCIe Base Specification 1.1
that includes PHY/MAC, Data Link, and Transaction layer circuitry embedded in the PCIe
hard IP blocks.
×1, ×4, and ×8 lane configurations
Built-in circuitry for electrical idle generation and detection, receiver detect, power state
transitions, lane reversal, and polarity inversion
8B/10B encoder and decoder, receiver synchronization state machine, and ±300 PPM
clock compensation circuitry
Options to use:
Compliant to IEEE P802.3ae specification
Embedded state machine circuitry to convert XGMII idle code groups (||I||) to and from
idle ordered sets (||A||, ||K||, ||R||) at the transmitter and receiver, respectively
8B/10B encoder and decoder, receiver synchronization state machine, lane deskew, and
±100 PPM clock compensation circuitry
Compliant to IEEE 802.3 specification
Automatic idle ordered set (/I1/, /I2/) generation at the transmitter, depending on the
current running disparity
8B/10B encoder and decoder, receiver synchronization state machine, and 100 parts per
million (PPM) clock compensation circuitry
Reverse bit slipper eliminates latency uncertainty to comply with CPRI/OBSAI
specifications
Optimized for power and cost for remote radio heads and RF modules
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■
Hard IP Data Link Layer and Transaction Layer
Hard IP Data Link Layer and custom Soft IP Transaction Layer
Arria II GX Transceiver Architecture
Feature Descriptions
Chapter 1: Arria II GX Device Family Overview
© July 2010 Altera Corporation
chapter.
Arria II GX Device Architecture
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