EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 76

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EP2AGX95EF29I5N

Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr

Specifications of EP2AGX95EF29I5N

Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2AGX95EF29I5N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2AGX95EF29I5N
Manufacturer:
ALTERA
0
4–16
Figure 4–8. 9-Bit Independent Multiplier Mode Shown for Half-DSP Block
Arria II GX Device Handbook, Volume 1
1
datab_1[8..0]
dataa_0[8..0]
datab_0[8..0]
dataa_1[8..0]
dataa_2[8..0]
datab_2[8..0]
dataa_3[8..0]
datab_3[8..0]
The multiplier operands can accept signed integers, unsigned integers, or a
combination of both. You can change the signa and signb signals dynamically and
can be registered in the DSP block. Additionally, the multiplier inputs and result can
be registered independently. You can use the pipeline registers in the DSP block to
pipeline the multiplier result, increasing the performance of the DSP block.
The round and saturation logic unit is supported for 18-bit independent multiplier
mode only.
clock[3..0]
ena[3..0]
aclr[3..0]
9
9
9
9
9
9
9
9
Half-DSP Block
signa
signb
Chapter 4: DSP Blocks in Arria II GX Devices
18
18
18
18
© July 2010 Altera Corporation
result_0[ ]
result_1[ ]
result_2[ ]
result_3[ ]
Operational Mode Descriptions

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