EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 186

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–2
LVDS Channels
Arria II GX Device Handbook, Volume 1
f
f
f
1
1
True mini-LVDS and RSDS inputs are not supported. The LVPECL I/O standard is
only for PLL clock inputs in differential mode.
For specifications and features of the differential I/O standards supported in
Arria II GX devices, refer to the
For specifications of the differential I/O standards supported in Arria II GX devices,
refer to the
In Arria II GX devices, there are true LVDS input buffers and LVDS I/O buffers at the
top, bottom, and right side of the device. The LVDS input buffers have 100- on-chip
differential termination (R
either LVDS input (without R
can configure the LVDS pins on the top, bottom, and right sides of the device, as
emulated LVDS output buffers, which use two single-ended output buffers with an
external resistor network to support LVDS, mini-LVDS, and RSDS standards.
Figure 8–1
the device is occupied by high-speed transceiver blocks.
When you configure the I/O buffers as LVDS input with R
set both the V
For more information about I/O banks, refer to the
chapter.
shows a high-level chip overview of Arria II GX devices. The left side of
Arria II GX Devices
CCIO
and V
CCPD
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II GX Devices
D
OCT) support. You can configure the LVDS I/O buffers as
to 2.5 V.
D
Datasheet.
OCT) or true LVDS output buffers. Alternatively, you
I/O Features in Arria II GX Devices
I/O Features in Arria II GX Devices
D
OCT enabled, you must
© July 2010 Altera Corporation
chapter.
LVDS Channels