EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 239
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 9: Configuration, Design Security, and Remote System Upgrades in Arria II GX Devices
Active Serial Configuration (Serial Configuration Devices)
Figure 9–8. Multi-Device AS Configuration When the Devices Receive the Same Data Using a Single .sof File
Notes to
(1) Connect the pull-up resistors to the V
(2) The MSEL pin settings vary for different configuration voltage standards and POR delay. To connect MSEL[3..0], refer to
(3) Connect the repeater buffers between the Arria II GX master and slave devices for DATA[0] and DCLK. This is to prevent any potential signal
(4) Arria II GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for DCLK.
Guidelines for Connecting Serial Configuration Device to Arria II GX Devices on Active
Serial Interface
Table 9–6. Maximum Trace Length and Loading for the AS Configuration
© July 2010
Arria II GX Devices AS Pins
DCLK
DATA[0]
nCSO
ASDO
Serial Configuration
integrity and clock skew problems.
Device
Figure
DATA
DCLK
Altera Corporation
ASDI
nCS
9–8:
V
CCIO (1)
10 kΩ
For single- and multi-device AS configurations, the board trace length and loading
between the supported serial configuration device and Arria II GX devices must
follow the recommendations listed in
V
CCIO (1)
Buffers (3)
10 kΩ
GND
V
CCIO (1)
CCIO
10 kΩ
power supply of I/O bank 3C.
DATA0
DCLK
nCSO
ASDO
nSTATUS
CONF_DONE
nCONFIG
nCE
Device Master
Maximum Board Trace Length from
the Arria II GX Devices to the Serial
Configuration Devices (Inches)
Arria II GX
CLKUSR
MSEL[3..0]
nCEO
N.C.
(2)
(4)
10
10
10
10
Table
GND
9–6.
Maximum Board Load (pF)
Arria II GX Device Handbook, Volume 1
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
nSTATUS
CONF_DONE
nCONFIG
nCE
DATA[0]
DCLK
Device Slave
Device Slave
15
30
30
30
Device Slave
Arria II GX
Arria II GX
Arria II GX
MSEL[3..0]
MSEL[3..0]
MSEL[3..0]
Table
nCEO
nCEO
nCEO
9–2.
N.C.
9–19
N.C.
N.C.
(2)
(2)
(2)
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