EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 30
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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2–4
LAB Control Signals
Figure 2–4. LAB-Wide Control Signals
Adaptive Logic Modules
Arria II GX Device Handbook, Volume 1
Dedicated Row LAB Clocks
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Each LAB contains dedicated logic for driving control signals to its ALMs, and has
two unique clock sources and three clock enable signals, as shown in
LAB control block can generate up to three clocks using the two clock sources and
three clock enable signals. Each LAB’s clock and clock enable signals are linked.
De-asserting the clock enable signal turns off the corresponding LAB-wide clock.
The ALM is the basic building block of logic in the Arria II GX architecture, providing
advanced features with efficient logic utilization. One ALM can implement any
function of up to six inputs and certain seven-input functions.
Each ALM drives all types of interconnects: local, row, column, carry chain, shared
arithmetic chain, register chain, and direct link interconnects.
high-level block diagram of the Arria II GX ALM.
6
6
6
labclk0
clock signals per LAB.
There are two unique
or asyncload
or labpreset
labclkena0
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Arria II GX Devices
labclk1
labclkena1
labclk2
labclkena2
syncload
© June 2009 Altera Corporation
Figure 2–5
labclr0
Adaptive Logic Modules
Figure
shows a
labclr1
2–4. The
synclr
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