XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 104

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 3: Phase-Matched Clock Dividers (PMCDs)
104
Figure 3-5
The release (REL) signal affects PMCD outputs in the following manner:
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RST asynchronously asserts.
Asserting REL synchronously starts the divided outputs toggling. REL is synchronous
to CLKA. Asserting REL must meet the setup time to CLKA.
REL assertion does not affect the delayed clock outputs.
REL is necessary when multiple PMCDs are used together and all PMCDs divided
outputs should toggle in phase.
REL is enabled with the EN_REL attribute. The default value of this attribute is
FALSE.
Set to TRUE only if multiple PMCDs are used together, or if other external
synchronization is needed.
RST must be Low before REL can have any effect.
The REL input is positive edge sensitive.
Once REL is asserted, the input has no further effect until another reset.
All output clocks forced Low.
Outputs
All CLK
CLKA
RST
illustrates an RST waveform when EN_REL = FALSE.
Figure 3-5: RST Waveform Example
www.xilinx.com
Deasserted RST is registered
After RST is registered,
all output clocks start toggling.
RST_DEASSERT_CLK = CLKA
EN_REL = FALSE
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
UG070_3_05_071404
R