XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 69

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
DESKEW_ADJUST Attribute
DFS_FREQUENCY_MODE Attribute
DLL_FREQUENCY_MODE Attribute
DUTY_CYCLE_CORRECTION Attribute
FACTORY_JF Attribute
PHASE_SHIFT Attribute
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The DESKEW_ADJUST attribute affects the amount of delay in the feedback path. The
possible values are SYSTEM_SYNCHRONOUS, SOURCE_SYNCHRONOUS,
0, 1, 2, 3, ..., or 31. The default value is SYSTEM_SYNCHRONOUS.
For most designs, the default value is appropriate. In a source-synchronous design, set this
attribute to SOURCE_SYNCHRONOUS. The remaining values should only be used after
consulting with Xilinx. For more information consult the
Setting”section.
The DFS_FREQUENCY_MODE attribute specifies the frequency mode of the digital
frequency synthesizer (DFS). The possible values are LOW and HIGH. The default value is
LOW. The frequency ranges for both frequency modes are specified in the
Sheet. DFS_FREQUENCY_MODE determines the frequency range of CLKIN, CLKFX, and
CLKFX180.
The DLL_FREQUENCY_MODE attribute specifies either the HIGH or LOW frequency
mode of the delay-locked loop (DLL). The default value is LOW. The frequency ranges for
both frequency modes are specified in the
The DUTY_CYCLE_CORRECTION attribute controls the duty cycle correction of the 1x
clock outputs: CLK0, CLK90, CLK180, and CLK270. The possible values are TRUE and
FALSE. The default value is TRUE. When set to TRUE, the 1x clock outputs are duty cycle
corrected to be within specified limits (see the
recommended to always set the DUTY_CYCLE_CORRECTION attribute to TRUE. Setting
this attribute to FALSE does not necessarily produce output clocks with the same duty
cycle as the source clock.
The Factory_JF attribute affects the DCMs jitter filter characteristics. This attribute controls
the DCM tap update rate. Factory_JF must be set to a specific value depending on the
DLL_FREQUENCY_MODE setting. The default value is F0F0 corresponding to
DLL_FREQUENCY_MODE = LOW (default). Factory_JF must be manually set to F0F0
when DLL_FREQUENCY_MODE = HIGH. The ISE® software tool will issue a warning if
FACTORY_JF is not set as stated.
The PHASE_SHIFT attribute determines the amount of phase shift applied to the DCM
outputs. This attribute can be used in both fixed or variable phase-shift mode. If used with
variable mode, the attribute sets the starting phase shift. When
CLKOUT_PHASE_SHIFT = VARIABLE_POSITIVE, the PHASE_SHIFT value range is 0 to
255. When CLKOUT_PHASE_SHIFT = VARIABLE_CENTER or FIXED, the
PHASE_SHIFT value range is –255 to 255. When CLKOUT_PHASE_SHIFT = DIRECT, the
PHASE_SHIFT value range is 0 to 1023. The default value is 0.
www.xilinx.com
Virtex-4 Data
Virtex-4 Data Sheet
Sheet.
“Source-Synchronous
for details). It is strongly
DCM Attributes
Virtex-4 Data
69