XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 6

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
04/10/07
08/10/07
04/10/08
06/17/08
12/01/08
Date
Version
2.2
2.3
2.4
2.5
2.6
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“Asynchronous Clocking,” page
operation.
Figure 6-6, page
“DCI in Virtex-4 FPGA Hardware,” page
outputs that do not require reference resistors on VRP/VRN.
Figure 7-10, page
Table
Figure
Table
Chapter 8, “Advanced SelectIO Logic
extensively revised and expanded with many new figures and tables.
Figure 2-5
Figure
Figure
“Frequency Synthesizer Characteristics” in Chapter
the LOCKED monitoring macro on recent step devices.
“SelectIO Resources Introduction” in Chapter
V
“DCI in Virtex-4 FPGA Hardware” in Chapter
standard.
“Lower Capacitance I/O Attributes” in Chapter
that do not have differential driver circuits.
Table
“Temperature Sensor Examples” in Chapter
temperature sensor.
Table 2-6, page
rows. Added descriptions to CLKFX_DIVIDE and CLKFX_MULTIPLY rows.
“DCM_AUTOCALIBRATION Attribute,” page
Figure 2-9, page 84
an effect.
Figure 4-11, page
Table 6-40, page
“REFCLK - Reference Clock,” page
to MHz.
Figure 7-21, page
Figure 2-4, page
“System-Synchronous Setting (Default),” page
describing cases when the DESKEW_ADJUST parameter has no effect.
REF
-dependent inputs are powered by V
7-9: Deleted Note (1).
7-12: Revised description of CE port.
6-43: Included FX family devices and added note (3) for Banks 9 and 10.
7-12: Added assumption that IOBDELAY_VALUE = 0 to text.
2-20: Corrected reset requirement from 3 periods to 200 ns.
2-22, associated text: Corrected number of clock cycles in Clock Event 4.
Figure 3-5, page
“IDELAY
and associated text: Updated.
“Cascading DCMs” in Chapter
65: Added CLK_FEEDBACK and DCM_AUTOCALIBRATION attribute
308: Added LVCMOS15_16_fast, LVDCI_DV2_18, and LVTTL24_fast.
73: Revised the contents of the DCM block.
238: Moved VREF to be inside the FPGA.
Timing”: Revised descriptions of Clock Events 1, 2, and 3 in
142: Removed REGCEN.
355: Corrected OFFDDRB labeling.
330: Updated figure title.
Table
and
“Note on Instability after an Increment/Decrement
www.xilinx.com
104: Clarified bullet regarding RST must be Low before REL has
Figure 2-11, page
6-40.
119: Added the results of performing a read and write
342: Changed IDELAYCTRL_REF_PRECISION units
Resources”: ISERDES and OSERDES sections
Revision
85: Removed element from Q output.
241: Added SSTL18_I_DCI to the list of DCI
CCAUX
9: Added information on Texas Instruments
6: Added note that differential and
6: Removed erroneous reference to SSTL3
2.
73: Added text to the end of the section
68: New section.
.
6: Added RSDS_25 to list of standards
2: Added note to indicate no need for
UG070 (v2.6) December 1, 2008
Operation”.
Figure
7-12.