XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 139

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Additional RAMB16 Primitive Design Considerations
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Data Parity Buses - DIP[A/B] and DOP[A/B]
Optional Output Registers
Independent Read and Write Port Width
RAMB16 Port Mapping Design Rules
R
The RAMB16 primitive is part of the Virtex-4 FPGA block RAM solution.
The data parity buses are additional pins used for data parity with incoming data into the
block RAM. The block RAM does not generate the parity bits for incoming data. These are
supplied by the user. If not supplying parity bits, the pins can be used for incoming data.
Optional output registers can be used at either or both A/B output ports of RAMB16. The
choice is made using the DO[A/B]_REG attribute. There is also an option to invert the
clocks for either or both of the A/B output registers using the
INVERT_CLK_DO[A/B]_REG attribute. The two independent clock enable pins are
REGCE[A/B]. When using the optional output registers at port [A|B], the synchronous
set/reset (SSR) pin of ports [A|B] can not be used.
register.
To specify the port widths, designers must use the READ_WIDTH_[A/B] and
WRITE_WIDTH_[A/B] attributes. The following rules should be considered:
•
•
•
The Virtex-4 FPGA block RAM can be configurable to various port widths and sizes.
Depending on the configuration, some data pins and address pins are not used.
page 125
Table
Designing a single port block RAM requires the port pair widths of one write and one
read to be set (e.g., READ_WIDTH_A and WRITE_WIDTH_A).
Designing a dual-port block RAM requires all port widths to be set.
When using these attributes, if both write ports or both read ports are set to 0, the
ISE® tools will not implement the design.
4-2, the following rules are useful to determine port connections:
);
// End of RAMB16_inst instantiation
shows the pins used in various configurations. In addition to the information in
.CLKB(CLKB),
.DIA(DIA),
.DIB(DIB),
.DIPA(DIPA),
.DIPB(DIPB),
.ENA(ENA),
.ENB(ENB),
.REGCEA(REGCEA), // 1-bit A port register enable input
.REGCEB(REGCEB), // 1-bit B port register enable input
.SSRA(SSRA),
.SSRB(SSRB),
.WEA(WEA),
.WEB(WEB)
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// 1-bit B port clock input
// 32-bit A port data input
// 32-bit B port data input
// 4-bit A port parity data input
// 4-bit B port parity data input
// 1-bit A port enable input
// 1-bit B port enable input
// 1-bit A port set/reset input
// 1-bit B port set/reset input
// 4-bit A port write enable input
// 4-bit B port write enable input
Additional RAMB16 Primitive Design Considerations
Figure 4-5
shows a optional output
Table 4-2,
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