XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 338

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 7: SelectIO Logic Resources
338
VHDL for Fixed Delay Mode
-- The IDELAYCTRL primitive must be instantiated in conjunction with the
-- IDELAY primitive when used in Fixed Delay Mode.
-- Module: IDELAY
-- Description: VHDL instantiation template
-- Fixed Delay Mode
--
-- Device: Virtex-4 Family
---------------------------------------------------------------------
-- Components Declarations
-- Component Declaration for IDELAY should be placed
-- after architecture statement but before "begin" keyword
component IDELAY
generic (
VARIABLE)
port (
end component;
-- Component Attribute specification for IDELAY
-- should be placed after architecture declaration but
-- before the "begin" keyword
--
-- Architecture Section
--
attribute IOBDELAY_TYPE : string;
attribute IOBDELAY_VALUE: integer;
-- Component Instantiation for IDELAY should be placed
-- in architecture after the "begin" keyword
--
-- Instantiation Section
--
U1 : IDELAY
generic map (
port map (
);
O : out STD_LOGIC;
I : in STD_LOGIC;
C : in STD_LOGIC;
CE : in STD_LOGIC;
INC : in STD_LOGIC;
RST : in STD_LOGIC
O => data_output,
I => data_input,
);
IOBDELAY_TYPE : string := "DEFAULT"; --(DEFAULT, FIXED,
IOBDELAY_VALUE : integer := 0 --(0 to 63)
);
IOBDELAY_TYPE => "FIXED", -- Set to FIXED for
IOBDELAY_VALUE => 31
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-- to the center of the delay element
-- Set the delay value equal
-- Fixed delay mode
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
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