XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 51

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Verilog Template
Declaring Constraints in UCF File
--Declaring constraints in VHDL file
attribute INIT_OUT
attribute PRESELECT_I0 : boolean;
attribute PRESELECT_I1 : boolean;
attribute LOC : string;
attribute INIT_OUT of U_BUFGMUX_VIRTEX4: label is 0;
attribute PRESELECT_I0 of U_BUFGMUX_VIRTEX4: label is FALSE;
attribute PRESELECT_I1 of U_BUFGMUX_VIRTEX4: label is FALSE;
attribute LOC of U_BUFGMUX_VIRTEX4: label is "BUFGCTRL_X#Y#";
--where # is valid integer locations of BUFGCTRL
//Example BUFGMUX_VIRTEX4 module declaration
module BUFGMUX_VIRTEX4 (O, I0, I1, S);
endmodule;
//Example BUFGCTRL instantiation
BUFGMUX_VIRTEX4 U_BUFGMUX_VIRTEX4 (
);
// Declaring constraints in Verilog
// synthesis attribute INIT_OUT of U_BUFGMUX_VIRTEX4 is 0;
// synthesis attribute PRESELECT_I0 of U_BUFGMUX_VIRTEX4 is FALSE;
// synthesis attribute PRESELECT_I1 of U_BUFGMUX_VIRTEX4 is FALSE;
// synthesis attribute LOC of U_BUFGMUX_VIRTEX4 is "BUFGCTRL_X#Y#";
// where # is valid integer locations of BUFGCTRL
INST "U_BUFGMUX_VIRTEX4" INIT_OUT = 0;
INST "U_BUFGMUX_VIRTEX4" PRESELECT_I0 = FALSE;
INST "U_BUFGMUX_VIRTEX4" PRESELECT_I1 = FALSE;
INST "U_BUFGMUX_VIRTEX4" LOC = BUFGCTRL_X#Y#;
where # is valid integer locations of BUFGCTRL
.O(user_o),
.I0(user_i0),
.I1(user_i1),
.S(user_s)
output O;
input
input
input
parameter INIT_OUT = 1'b0;
parameter PRESELECT_I0 = "TRUE";
parameter PRESELECT_I1 = "FALSE";
I0;
I1;
S;
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: integer;
VHDL and Verilog Templates
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