XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 220

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Configurable Logic Blocks (CLBs)
220
Verilog Template
component RAM16X1S
end component;
--
---------------------------------------------------------------------
--
-- Architecture section:
--
-- Attributes for RAM initialization ("0" by default):
attribute INIT: string;
--
attribute INIT of U_RAM16X1S: label is "0000";
--
-- Distributed RAM Instantiation
U_RAM16X1S: RAM16X1S
--
---------------------------------------------------------------------
//
// Module: RAM_16S
//
// Description: Verilog instantiation template
//
//
//
//
// Device: Virtex-4 Family
//
//-------------------------------------------------------------------
//Distributed RAM Instantiation
RAM16X1S U_RAM16X1S (
);
port (
port map (
generic (
D
WE
WCLK
A0
A1
A2
A3
O
INIT : bit_vector := X"0000"
);
D
WE
WCLK : in std_logic;
A0
A1
A2
A3
O
);
=> , -- insert input signal
=> , -- insert Write Enable signal
=> , -- insert Write Clock signal
=> , -- insert Address 0 signal
=> , -- insert Address 1 signal
=> , -- insert Address 2 signal
=> , -- insert Address 3 signal
=>
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: in std_logic;
: out std_logic
Distributed RAM
Single Port 16 x 1
can be used also for RAM16X1S_1
-- insert output signal
.WCLK(),
.WE(),
.A0(),
.A1(),
www.xilinx.com
.D(),
// insert Write Clock signal
// insert Write Enable signal
// insert Address 0 signal
// insert Address 1 signal
// insert input signal
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R