XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 127

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Block RAM Address Mapping
Table 4-3: Port Address Mapping
Block RAM Attributes
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Width
16 + 2
32 + 4
8 + 1
Port
1
2
4
Locations
3 2 1 0
1
Parity
N.A.
0
Content Initialization - INIT_xx
R
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15
7
Each port accesses the same set of 18,432 memory cells using an addressing scheme
dependent on the width of the port. The physical RAM locations addressed for a particular
width are determined using the following formula (of interest only when the two ports use
different aspect ratios):
Table 4-3
All attribute code examples are shown in the
section. Further information on using these attributes is available in the
RAMB16 Primitive Design Considerations”
INIT_xx attributes define the initial memory contents. By default block RAM memory is
initialized with all zeros during the device configuration sequence. The 64 initialization
attributes from INIT_00 through INIT_3F represent the regular memory contents. Each
INIT_xx is a 64-digit hex-encoded bit vector. The memory contents can be partially
initialized and are automatically completed with zeros.
The following formula is used for determining the bit positions for each INIT_xx attribute.
Given yy = conversion hex-encoded to decimal (xx), INIT_xx corresponds to the memory
cells as follows:
•
•
For example, for the attribute INIT_1F, the conversion is as follows:
•
•
•
More examples are given in
14
END = ((ADDR + 1) * Width) - 1
START= ADDR * Width
from [(yy + 1) * 256] – 1
to (yy) * 256
yy = conversion hex-encoded to decimal X”1F” = 31
from [(31+1) * 256] – 1 = 8191
to 31 * 256 = 7936
3
13
shows low-order address mapping for each port width.
6
12
1
11
www.xilinx.com
5
Table
10
4-4.
Data Locations
2
9
0
4
section.
8
“Block RAM VHDL and Verilog Templates”
7
3
Block RAM Address Mapping
6
1
5
2
0
“Additional
4
3
1
2
0
1
0
127
0