XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 158

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
158
Case 1: Writing to an Empty FIFO
Prior to the operations performed in
Clock Event 1 and Clock Event 3: Write Operation and Deassertion of EMPTY
Signal
During a write operation to an empty FIFO, the content of the FIFO at the first address is
replaced by the data value on the DI pins. Three read-clock cycles later (four read-clock
cycles for FWFT mode), the EMPTY pin is deasserted when the FIFO is no longer empty.
For the example in
event 1 is with respect to the write-clock, while clock event 3 is with respect to the read-
clock. Clock event 3 appears four read-clock cycles after clock event 1.
•
•
•
•
If the rising WRCLK edge is close to the rising RDCLK edge, EMPTY could be deasserted
one RDCLK period later.
Clock Event 2 and Clock Event 4: Write Operation and Deassertion of
ALMOSTEMPTY Signal
Three read-clock cycles after the fourth data is written into the FIFO, the ALMOSTEMPTY
pin is deasserted to signify that the FIFO is not in the ALMOSTEMPTY state.
AEMPTY
WRCLK
EMPTY
RDCLK
WREN
RDEN
At time T
inputs of the FIFO.
At time T
the WREN input of the FIFO.
At time T
output pins of the FIFO. In the case of standard mode, data 00 does not appear at the
DO output pins of the FIFO.
At time T
of standard mode, EMPTY is deasserted one read-clock earlier than clock event 3.
DO
DI
FDCK_DI
FCCK_WREN
FCKO_DO
FCKO_EMPTY
Figure 4-17: Writing to an Empty FIFO in FWFT Mode
Figure
, before clock event 1 (WRCLK), data 00 becomes valid at the DI
, after clock event 3 (RDCLK), data 00 becomes valid at the DO
1
00
, before clock event 1 (WRCLK), write enable becomes valid at
, after clock event 3 (RDCLK), EMPTY is deasserted. In the case
www.xilinx.com
4-17, the timing diagram is drawn to reflect FWFT mode. Clock
T
T
FCCK_WREN
FDCK_DI
01
Figure
4-17, the FIFO is completely empty.
02
2 3
03
T
UG070 (v2.6) December 1, 2008
T
FDCK_DI
FCKO_AEMPTY
00
Virtex-4 FPGA User Guide
T
04
FCKO_EMPTY
T
FCKO_DO
05
ug070_4_17_071204
4
06
R