XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 204

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 5: Configurable Logic Blocks (CLBs)
CLB / Slice Timing Models
204
Arithmetic Logic
The arithmetic logic includes an XOR gate that allows a 2-bit full adder to be implemented
within a slice. In addition, a dedicated AND (FAND or GAND) gate (shown in
improves the efficiency of multiplier implementation.
Due to the large size and complexity of Virtex-4 FPGAs, understanding the timing
associated with the various paths and functional elements has become a difficult and
important task. Although it is not necessary to understand the various timing parameters
to implement most designs using Xilinx software, a thorough timing model can assist
advanced users in analyzing critical paths or planning speed-sensitive designs.
Three timing model sections are described.
•
•
•
Use the models in this chapter in conjunction with both the Xilinx Timing Analyzer
software (TRCE) and the section on switching characteristics in the
pin names, parameter names, and paths are consistent with the post-route timing and pre-
route static timing reports. Most of the timing parameters found in the section on
switching characteristics are described in this chapter.
All timing parameters reported in the
configurable logic blocks (CLBs). The following sections correspond to specific switching
characteristics sections in the
•
•
•
•
Functional element diagram - basic architectural schematic illustrating pins and
connections.
Timing parameters - definitions of
Timing Diagram - illustrates functional element timing parameters relative to each
other.
“General Slice Timing Model and Parameters”
“Slice Distributed RAM Timing Model and Parameters (Available in SLICEM only)”
(CLB Distributed RAM Switching Characteristics)
“Slice SRL Timing Model and Parameters (Available in SLICEM only)”
Switching Characteristics)
“Slice Carry-Chain Timing Model and Parameters”
Characteristics)
www.xilinx.com
Virtex-4 Data
Virtex-4 Data Sheet
Virtex-4 Data Sheet
Sheet:
(CLB Switching Characteristics)
(CLB Application Switching
are associated with slices and
timing parameters.
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
Virtex-4 Data
(CLB SRL
Figure
Sheet. All
5-2)
R