XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 215

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Table 5-8: Slice Carry-Chain Timing Parameters
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Parameter
Sequential Delays for Slice LUT Configured as Carry Chain
T
T
T
T
T
T
T
T
T
Setup/Hold Times for Slice LUT Configured as Carry Chain
T
T
T
T
BXCY
BYCY
BYP
FANDCY
GANDCY
OPCYF
OPCYG
OPX
OPY
xxS
xxH
CINCK
CKCIN
= Setup time (before clock edge)
/
= Hold time (after clock edge)
/
/
/
/
R
BX/BY input to C
output
C
F/G input to C
F/G input to C
F/G input to
XMUX/YMUX output
C
IN
IN
input to C
Data inputs (DI)
Slice Carry-Chain Timing Parameters
Slice Carry-Chain Timing Characteristics
Function
Table 5-8
Figure
Figure 5-27
Virtex-4 FPGA slice.
•
OUT
OUT
OUT
At time T
input of the slice register. This is reflected on either the XQ or YQ pin at time T
after clock event 1.
OUT
5-26.
output
output
output
shows the slice carry-chain timing parameters for a majority of the paths in
illustrates the timing characteristics of a slice carry chain implemented in a
CINCK
Figure 5-27: Slice Carry-Chain Timing Characteristics
(RESET)
Propagation delay from the BX/BY inputs of the slice, to C
slice.
Propagation delay from the C
Propagation delay from the F/G inputs of the slice, to C
slice using FAND (product).
Propagation delay from the F/G input of the slice to C
Propagation delay from the F/G inputs of the slice, to XMUX/YMUX output
of the slice using XOR (sum).
The following descriptions are for setup times only.
stable at the D-input of the slice sequential elements (configured as a flip-
flop).
Time before Clock (CLK) that data from the C
(DATA)
(OUT)
CLK
C
YQ
SR
before clock event 1, data from C
IN
Figure 5-27
www.xilinx.com
1
T
shows the worst-case path.
CINCK
T
CKO
2
IN
Description
input of the slice, to C
IN
input becomes valid-High at the D
3
T
IN
RCK
CLB / Slice Timing Models
input of the slice must be
ug070_5_27_080204
T
CKO
OUT
OUT
OUT
output of the slice.
output of the slice.
OUT
output of the
output of the
CKO
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