XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 62

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Digital Clock Managers (DCMs)
62
Clock Output Ports
Dynamic Reconfiguration Write Enable Input — DWE
Dynamic Reconfiguration Enable Input — DEN
1x Output Clock — CLK0
1x Output Clock, 90° Phase Shift — CLK90
1x Output Clock, 180° Phase Shift — CLK180
1x Output Clock, 270° Phase Shift — CLK270
2x Output Clock — CLK2X
The dynamic reconfiguration write enable (DWE) input pin provides the write enable
control signal to write the DI data into the DADDR address. When not used, it must be tied
Low. See the Dynamic Reconfiguration chapter of the
information.
The dynamic reconfiguration enable (DEN) input pin provides the enable control signal to
access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is
not used, DEN must be tied Low. When DEN is tied Low, DO reflects the DCM status
signals. See the Dynamic Reconfiguration chapter of the
more information.
A DCM provides nine clock outputs with specific frequency and phase relationships.
When CLKFB is connected, all DCM clock outputs have a fixed phase relationship to
CLKIN. When CLKFB is not connected, the DCM outputs are not phase aligned. However,
the phase relationship between all output clocks is preserved.
The CLK0 output clock provides a clock with the same frequency as the DCM’s effective
CLKIN frequency. By default, the effective input clock frequency is equal to the CLKIN
frequency. The CLKIN_DIVIDE_BY_2 attribute is set to TRUE to make the effective CLKIN
frequency ½ the actual CLKIN frequency. The
provides further information. When CLKFB is connected, CLK0 is phase aligned to
CLKIN.
The CLK90 output clock provides a clock with the same frequency as the DCM’s CLK0
only phase-shifted by 90°.
The CLK180 output clock provides a clock with the same frequency as the DCM’s CLK0
only phase-shifted by 180°.
The CLK270 output clock provides a clock with the same frequency as the DCM’s CLK0
only phase-shifted by 270°.
The CLK2X output clock provides a clock that is phase aligned to CLK0, with twice the
CLK0 frequency, and with an automatic 50/50 duty-cycle correction. Until the DCM is
locked, the CLK2X output appears as a 1x version of the input clock with a 25/75 duty
cycle. This behavior allows the DCM to lock on the correct edge with respect to the source
clock.
www.xilinx.com
CLKIN_DIVIDE_BY_2 Attribute
Virtex-4 Configuration Guide
Virtex-4 Configuration Guide
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
description
for more
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