XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 168

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
168
Status Flags
Resource Utilization
Performance Expressed in Maximum Read and/or Write Clock Frequency
CORE Generator Tool Implementation
Although the functionality of the status flags on the composite FIFO remain the same, the
assertion/deassertion latencies for some of the signals have increased. The assertion
values for key signals have remained the same as on the FIFO16 (EMPTY, FULL,
ALMOSTEMPTY, ALMOSTFULL, RDERR, and WRERR).
values for the status flags. Also note that the values have an uncertainty that is affected by
the frequency ratios of the read/write clock, as well as the read/write patterns.
Table 4-16: Clock Cycle Latency for Status Flag Assertion and Deassertion
The design was implemented using the ISE 8.1i software with default settings for MAP,
Place, and Route. The approximate LUT count for a x4 design varies from 55 to 70 LUTs.
For a x9 design, the LUT count varies from 65 to 80 LUTs, and for a x18 design the LUT
count varies from 85 to 100 LUTs. The LUT count for a x36 design varies from 125 to 130
LUTs.
The maximum read and/or write clock rate is >500 MHz for all configurations and modes,
except for the 512 x 36 configuration with write clock > read clock, where the max
frequency for standard mode is 473 MHz, and for FWFT mode it is 488 MHz.
The CORE Generator tool should be used to implement this solution. FIFO Generator (v3.2
and above) automatically implements the work-arounds detailed above. The device
utilization is detailed in the core data sheet, which can be accessed from:
http://www.xilinx.com/bvdocs/ipcenter/data_sheet/fifo_generator_ds317.pdf
Both synchronous and asynchronous FIFOs can be implemented using FIFO Generator
block RAM FIFOs available from the CORE Generator tool instead of using the FIFO16
primitives. The block RAM-based implementations are slower than FIFO16-based
implementations because the FIFO control logic is implemented in the fabric of the device.
Notes:
1. Latency values in bold vary with the ratio between the read/write clock frequencies and read/write
EMPTY
FULL
ALMOSTEMPTY
ALMOSTFULL
RDERR
WRERR
Clock Cycle Latency
pattern. In certain conditions for WRCLK > RDCLK, the ALMOSTEMPTY flag deasserts before the
EMPTY flag. This behavior is reflected in simulations, and increasing the ALMOST_EMPTY_OFFSET
rectifies the behavior.
Clock Style
FIFO Type
www.xilinx.com
Assertion
WRCLK > RDCLK
10
0
1
1
0
0
Deassertion
10 / 12
9
4
9
0
0
Standard/FWFT
(1)
Table 4-16
UG070 (v2.6) December 1, 2008
Assertion
RDCLK > WRCLK
Virtex-4 FPGA User Guide
11
0
0
1
0
0
lists the latency
Deassertion
10 / 11
10
9
5
0
0
R