XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 59

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

DCM Ports
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Clock Input Ports
R
Source Clock Input — CLKIN
Feedback Clock Input — CLKFB
There are four types of DCM ports available in the Virtex-4 architecture:
•
•
•
•
The source clock (CLKIN) input pin provides the source clock to the DCM. The CLKIN
frequency must fall in the ranges specified in the
comes from one of the following buffers:
1.
2.
3.
The feedback clock (CLKFB) input pin provides a reference or feedback signal to the DCM
to delay-compensate the clock outputs, and align them with the clock input. To provide the
necessary feedback to the DCM, connect only the CLK0 DCM output to the CLKFB pin.
When the CLKFB pin is connected, all clock outputs are deskewed to CLKIN. When the
CLKFB pin is not connected, DCM clock outputs are not deskewed to CLKIN. However,
the relative phase relationship between all output clocks is preserved.
During internal feedback configuration, the CLK0 output of a DCM connects to a global
buffer on the same top or bottom half of the device. The output of the global buffer
connects to the CLKFB input of the same DCM.
During the external feedback configuration, the following rules apply:
1.
2.
Figure 2-9
forwarding with external feedback configuration.
The feedback clock input signal can be driven by one of the following buffers:
Clock Input Ports
Control and Data Input Ports
Clock Output Ports
Status and Data Output Ports
IBUFG – Global Clock Input Buffer
The DCM compensates for the clock input path when an IBUFG on the same edge (top
or bottom) of the device as the DCM is used.
BUFGCTRL – Internal Global Clock Buffer
Any BUFGCTRL can drive any DCM in the Virtex-4 device using dedicated global
routing. A BUFGCTRL can drive the DCM CLKIN pin when used to connect two
DCMs in series.
IBUF – Input Buffer
When an IBUF drives the CLKIN input, the PAD to DCM input skew is not
compensated.
To forward the clock, the CLK0 of the DCM must directly drive an OBUF or a BUFG-
to-DDR configuration.
External to the FPGA, the forwarded clock signal must be connected to the IBUFG
(GCLK pin) or the IBUF driving the CLKFB of the DCM. Both CLK and CLKFB should
have identical I/O buffers.
and
Figure
2-10, in
www.xilinx.com
“Application Examples,” page
Virtex-4 Data
82, illustrate clock
Sheet. The clock input signal
DCM Ports
59