XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 3

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

UG070 (v2.6) December 1, 2008
09/12/05
03/21/06
10/06/06
04/11/05
Date
Version
1.3
1.4
1.5
1.6
Chapter 1: Revised
section including
Chapter 2: Revised FACTORY_JF value in
section. Clarified global clock discussion in
“Clock Capable
Chapter 4: Added
and
Chapter 5: Revised
Chapter 6: Revised
Chapter 7: Revised
Chapter 8: Added
Revised
Chapter 2: Revised FACTORY_JF value in
description is updated in
Chapter 6: Revised the
Chapter 8: Added more information to
Chapter 1: Updated description under
Chapter 4: Changed
NO_CHANGE Mode
application example.
Chapter 5: Revised slice label in
Chapter 6: Added to the
“PULLUP/PULLDOWN/KEEPER for IBUF, OBUFT, and IOBUF”
numbers in the +1.5V column in
notes 4 and 5 to
page
page 259
text above table. Added HSLVDCI to
FF668 in
Chapter 8: Revised
Chapter 9, “Temperature Sensing
Chapter 7, “SelectIO Logic
Clock”
Figure 4-8, page
306. Added
and deleted former Table 7-10.
“Guidelines for Using the Bitslip Submodule”
Table
section. Added 1.2V to
6-43.
I/O”.
Table 6-38, page
“HSLVDCI (High-Speed Low Voltage Digitally Controlled Impedance),”
Figure 1-21, page
“Built-in Block RAM Error Correction Code”
“ISERDES Latencies,” page 379
Table 1-1, page
Table 5-1
Table 6-29, page
“REFCLK - Reference Clock”
“Clock Enable Inputs – CE1 and
Table 4-8, page 144
123.
and
“Simultaneous Switching Output Limits”
“Xilinx DCI”
www.xilinx.com
Figure 2-20
Cascadable Block RAM
Resources”: Modified text in section
and
Table 6-5, page
Figure 5-30, page
Table 6-40, page
299. Updated 3.3V I/O Design Guidelines
Table 5-2, page
Diode”: Added the Virtex-4 temperature-sensing diode.
26,
43.
290.
and
Table 6-42, page
Figure
section. Added IBUF to the
Table
“Clock Enable Inputs – CE1 and CE2,” page
and added a note. Updated the discussions in
Revision
Table 2-6, page
Figure
Table 2-6, page
“Global Clock
1-1. Updated
1-14, and
258. Corrected
184.
2-21.
and added
308, and added link to SSO calculator to
224.
and
sections. Removed synchronous FIFO
CE2”.
310. Revised Virtex-4 (SX Family)
“BUFR Attributes and Modes”
“OSERDES Latencies,” page
section.
65. Added
65. The LOCKED signal
Figure 1-21, page
Buffers”,
Table 7-10, page
Figure 6-70, page
“REFCLK - Reference
section. Revised
section.
Virtex-4 FPGA User Guide
discussion. Added V
“Phase-Shift Overflow”
“Clock
Regions”, and
“Summary,”
43.
326.
292. Added
Figure 4-6
394.
369.
CCO