XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 71

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Input Clock Requirements
Input Clock Changes
To provide the correct clock deskew, the DCM depends on the dedicated routing and
resources used at the clock source and feedback input. An additional delay element (see
“Deskew
tools analyze the routing around the DCM to determine if a delay must be inserted to
compensate for the clock source or feedback path. Thus, using dedicated routing is
required to achieve predictable deskew. All nine DCM output clocks are deskewed when
the CLKFB pin is used.
The clock input of the DCM can be driven either by an IBUFG/IBUFGDS, IBUF,
BUFGMUX, or a BUFGCNTL. Since there is no dedicated routing between an IBUF and a
DCM clock input, using an IBUF causes additional input delay that is not compensated by
the DCM.
The DCM output clock signal is essentially a delayed version of the input clock signal. It
reflects any instability on the input clock in the output waveform. The DCM input clock
requirements are specified in the
Once locked, the DCM can tolerate input clock period variations of up to the value
specified by CLKIN_PER_JITT_DLL_HF (at high frequencies) or
CLKIN_PER_JITT_DLL_LF (at low frequencies). Larger jitter (period changes) can cause
the DCM to lose lock, indicated by the LOCKED output deasserting. The user must then
reset the DCM. The cycle-to-cycle input jitter must be kept to less than
CLKIN_CYC_JITT_DLL_LF in the low frequencies and CLKIN_CYC_JITT_DLL_HF for
the high frequencies.
Changing the period of the input clock beyond the maximum input period jitter
specification requires a manual reset of the DCM. Failure to reset the DCM produces an
unreliable LOCKED signal and output clock. It is possible to temporarily stop the input
clock and feedback clock with little impact to the deskew circuit, as long as CLKFX or
CLKFX180 is not used.
If the input clock is stopped and CLKFX or CLKFX180 is used, the CLKFX or CLKFX180
outputs might stop toggling, and DO[2] (CLKFX Stopped) is asserted. The DCM must be
reset to recover from this event.
The DO[2] CLKFX stopped status is asserted in 257 to 260 CLKIN cycles after CLKFX is
stopped. CLKFX does not resume and DO[2] will not deassert until the DCM is reset.
In any other case, the clock should not be stopped for more than 100 ms to minimize the
effect of device cooling; otherwise, the tap delays might change. The clock should be
stopped during a Low or a High phase, and must be restored with the same input clock
period/frequency. During this time, LOCKED stays High and remains High when the
Adjust”) is available to compensate for the clock source or feedback path. The ISE
CLKIN
www.xilinx.com
Figure 2-3: Simplified DLL Circuit
Control
Delay Line
Virtex-4 Data
Variable
CLKFB
CLKOUT
Sheet.
Distribution
Network
UG070_2_03_060508
Clock
DCM Design Guidelines
71