XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 134

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
134
RAMB16 Verilog Template
//
//
//
//
//
//
//
//
registers
registers
cascaded
cascaded
"NO_CHANGE"
"NO_CHANGE"
of the RAM
);
-- End of RAMB16_inst instantiation
// RAMB16: Virtex-4 16k+2k Parity Paramatizable Block RAM
// Virtex-4 FPGA User Guide
RAMB16 #(
declaration
<-----Cut code below this line---->
// The following INIT_xx declarations specify the initial contents
instance
.DOA_REG(0),
.DOB_REG(0),
.INIT_A(36'h000000000),
.INIT_B(36'h000000000),
.INVERT_CLK_DOA_REG("FALSE"),// Invert clock on A port output
.INVERT_CLK_DOB_REG("FALSE"),// Invert clock on A port output
.RAM_EXTENSION_A("NONE"),
.RAM_EXTENSION_B("NONE"),
.READ_WIDTH_A(0),
.READ_WIDTH_B(0),
.SRVAL_A(36'h000000000), // Set/Reset value for A port output
.SRVAL_B(36'h000000000),
.WRITE_MODE_A("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or
.WRITE_MODE_B("WRITE_FIRST"), // "WRITE_FIRST", "READ_FIRST", or
.WRITE_WIDTH_A(0),
.WRITE_WIDTH_B(0),
Verilog
DIPA => DIPA,
DIPB => DIPB,
ENA => ENA,
ENB => ENB,
REGCEA => REGCEA, -- 1-bit A port register enable input
REGCEB => REGCEB, -- 1-bit B port register enable input
SSRA => SSRA,
SSRB => SSRB,
WEA => WEA,
WEB => WEB
("TRUE" or "FALSE")
("TRUE" or "FALSE")
code
RAMB16
: the following instance declaration needs to be placed
: parenthesis can be changed to properly reference and
: To incorporate this function into the design,
: in the body of the design code. The instance name
: (RAMB_inst) and/or the port declarations within the
: connect this function to the design. All inputs
: and outputs must be connected.
www.xilinx.com
// Optional output registers on A port (0 or 1)
// Optional output registers on B port (0 or 1)
-- 4-bit
-- 4-bit
-- 1-bit
-- 1-bit
-- 1-bit
-- 1-bit
-- 4-bit
-- 4-bit
// Valid values are 1, 2, 4, 9, 18, or 36
// Valid values are 1, 2, 4, 9, 18, or 36
// Valid values are 1, 2, 4, 9, 18, or 36
// Valid values are 1, 2, 4, 9, 18, or 36
// Initial values on A output port
// Initial values on B output port
// Set/Reset value for B port output
// "UPPER", "LOWER" or "NONE" when
// "UPPER", "LOWER" or "NONE" when
A port parity Input
B port parity Input
A port Enable Input
B port Enable Input
A port Synchronous Set/Reset Input
B port Synchronous Set/Reset Input
A port Write Enable Input
B port Write Enable Input
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
R