XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 183

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Configurable Logic Blocks (CLBs)
CLB Overview
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
The Configurable Logic Blocks (CLBs) are the main logic resource for implementing
sequential as well as combinatorial circuits. Each CLB element is connected to a switch
matrix to access to the general routing matrix (shown in
contains four interconnected slices. These slices are grouped in pairs. Each pair is
organized as a column. SLICEM indicates the pair of slices in the left column, and SLICEL
designates the pair of slices in the right column. Each pair in a column has an independent
carry chain; however, only the slices in SLICEM have a common shift chain.
The Xilinx® tools designate slices with the following definitions. An “X” followed by a
number identifies a column of slices. The number counts up in sequence from the left to the
right. A “Y” followed by a number identifies the position of each slice in a pair as well as
the CLB row. The “Y” number counts slices starting from the bottom in sequence: 0, 1, 0, 1
(the first CLB row); 2, 3, 2, 3 (the second CLB row); etc.
the bottom-left corner of the die. Slices X0Y0 and X0Y1 constitute the SLICEM column-pair,
and slices X1Y0 and X1Y1 constitute the SLICEL column-pair. For each CLB, SLICEM
indicates the pair of slices labeled with an even number – SLICE(0) or SLICE(2), and
SLICEL designates the pair of slices with an odd number – SLICE(1) or SLICE(3).
(Logic or Distributed RAM or Shift Register)
Switch
Matrix
Figure 5-1: Arrangement of Slices within the CLB
CLB
SHIFTOUT
SHIFTIN
www.xilinx.com
SLICE (2)
SLICE (0)
X0Y1
X0Y0
COUT
CIN
SLICEM
SLICEL
(Logic Only)
SLICE (3)
SLICE (1)
Figure 5-1
X1Y1
X1Y0
Figure
COUT
CIN
5-1). A CLB element
shows the CLB located in
Chapter 5
ug070_5_01_071504
to Neighbors
Interconnect
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