XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 307

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Nominal PCB Specifications
R
PCB Construction
Signal Return Current Management
Load Traces
Power Distribution System Design
The maximum ratio of I/O to V
this reason, most of the SSO limits (those higher than eight per V
for sparse-chevron packages. The SSO limits table,
standards with limits less than eight (per V
other I/O standards are designated “no limit” for the nominal PCB case.
For boards that do not meet the nominal PCB requirements listed in
Specifications”, the Virtex-4 FPGA SSO calculator is available, containing all SSO limit data
for all I/O standards. For designs in nominal PCBs mixing limited and “no limit” I/O
standards, the Virtex-4 FPGA SSO calculator must be used to ensure that I/O utilization
does not exceed the limit. Information on the calculator is available under the
SSO Calculator”
The nominal SSO tables
PCB parameters meet the following requirements. In cases where PCB parameters do not
meet all requirements listed below, the Virtex-4 FPGA SSO calculator must be used to
determine the SSO limit, according to the physical factors of the unique PCB.
•
•
•
•
•
•
•
•
•
V
Total board thickness must be no greater than 62 mils (1575 μ).
Traces must be referenced to a plane on an adjacent PCB layer.
The reference plane must be either GND or the V
driver.
The reference layer must remain uninterrupted for its full length from device to
device.
All IOB output buffers must drive controlled impedance traces with characteristic
impedance of 50Ω ±10%.
Total capacitive loading at the far end of the trace (input capacitance of receiving
device) must be no more than 10 pF.
Designed according to Chapter 4 of the
♦
♦
♦
♦
V
CCO
CCO
At least one decoupling capacitor per V
Parameters of the FPGA”)
No less than one of each capacitor value present (see “Step 2: Designing the
Generic Bypassing Network”)
Capacitors mounted within a distance of λ/40 (see “Capacitor Placement”)
Approved solder land patterns (see B, C, and D of Figure 4-6, “Example Capacitor
Land and Mounting Geometries”)
and GND vias should have a drill diameter no less than 11 mils (279 μ).
and GND planes cannot be separated by more than 5.0 mils (152 μ)
section.
(Table 6-40
www.xilinx.com
CCO
/GND pin pairs in sparse-chevron packages is 8:1. For
and
Table
CCO
Virtex-4 PCB Designer’s
6-42) contain SSO limits for cases where the
/GND pair) appear in the table. All the
CCO
Simultaneous Switching Output Limits
Table
pin (see “Step 1: Determining Critical
CCO
6-40, reflects this. Only I/O
associated with the output
CCO
Guide.
/GND pair) are moot
“Nominal PCB
“Full Device
307