XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 116

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
Block RAM Introduction
Synchronous Dual-Port and Single-Port RAMs
116
Data Flow
•
•
•
In addition to distributed RAM, Virtex-4 devices feature a large number of 18 Kb block
RAM memories. True Dual-Port™ RAM offers fast blocks of memory in the device. Block
RAMs are placed in columns, and the total number of block RAM memory depends on the
size of the Virtex-4 device. The 18 Kb blocks are cascadable to enable a deeper and wider
memory implementation, with a minimal timing penalty.
Embedded dual- or single-port RAM modules, ROM modules, synchronous FIFOs, and
data width converters are easily implemented using the Xilinx® CORE Generator™
software memory modules. Asynchronous FIFOs can be generated using the CORE
Generator tool FIFO Generator module. The synchronous or asynchronous FIFO
implementation does not require additional CLB resources for the FIFO control logic since
it uses dedicated hardware resources.
The 18 Kb block RAM dual-port memory consists of an 18 Kb storage area and two
completely independent access ports, A and B. The structure is fully symmetrical, and both
ports are interchangeable.
port names and descriptions.
Data can be written to either or both ports and can be read from either or both ports. Each
write operation is synchronous, each port has its own address, data in, data out, clock,
clock enable, and write enable. The read operation is synchronous and requires a clock
edge.
There is no dedicated monitor to arbitrate the effect of identical addresses on both ports. It
is up to the user to time the two clocks appropriately. However, conflicting simultaneous
writes to the same location never cause any physical damage.
When a block RAM port is enabled, all address transitions must meet the setup/hold time
of the ADDR inputs with respect to the port clock, as listed in the
requirement must be met even when the read data output is of no interest and ignored by
the user.
A read operation requires one clock edge.
DO has an optional internal pipeline register.
Data input and output signals are always described as buses; that is, in a 1-bit width
configuration, the data input signal is DI[0] and the data output signal is DO[0].
www.xilinx.com
Figure 4-1
illustrates the dual-port data flow.
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
Virtex-4 Data
Table 4-1
Sheet. The
lists the
R