XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 175

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Flag AF1, AF2, or AF3 goes High if the read sector (RAgray) is equal to write counter sector
one, two, or three respectively. A High on one of these flags sets the ALMOSTFULL flag
High as shown in
Because the circuit is operating in two clock domains (RDCLK and WRCLK), there is a
possibility that the OR of AF1, AF2, and AF3 could spike FALSE as one of these signals
transitions FALSE and another transitions TRUE. To prevent ALMOSTFULL from
erroneously going FALSE when this occurs, a flip-flop is added to the circuit. This flip-flop
adds the requirement that the OR output must be FALSE for two consecutive WRCLK
periods for ALMOSTFULL to go FALSE. The ALMOSTEMPTY circuit works in a similar
fashion.
The FULL flag goes true when the above ALMOSTFULL flag conditions are true AND the
next most significant bit of WRCOUNT is a one.
If WRCLK is halted, ALMOSTFULL and FULL are frozen in their current states. When
WRCLK restarts, these flags can switch, subject to the delays specified above. (Note that
this is the behavior of all asynchronous FIFOs, because the ALMOSTFULL and FULL flags
are always synchronous to the write clock.)
The ALMOSTEMPTY flag goes true if the current read sector is equal to the current write
sector, or if the current read sector is equal to the current write sector – 1. ALMOSTEMPTY
flag is generated similar to the ALMOSTFULL flag and is shown in
Setting of the ALMOSTEMPTY flag occurs between two and three RDCLK periods after an
equality comparison goes true.
RDCLK
RST
AF1
AF2
AF3
[msb:msb-3]
RDCOUNT
Figure 4-32: ALMOSTFULL and FULL Flag Generation
LUT
Figure
Binary → Gray
IN[3:0]
D
RST
4-32.
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Q
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
IN
OUT
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000
OUT[3:0]
4 LUTs
LUT
WRCOUNT[msb-4]
FIFO16 Error Condition and Work-Arounds
[3:0]
LUT
RDCLK
D[3:0] Q[3:0]
D
D
RST
RST
RST
Figure
Q
Q
[3:0] RAgray[3:0]
4-33.
UG070_c4_33_020607
ALMOSTFULL
FULL
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