XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 28

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 1: Clock Resources
28
Global Clock Buffer Primitives
subsections detail the various configurations, primitives, and use models of the Virtex-4
FPGA clock buffers.
The primitives in
Table 1-3: Global Clock Buffer Primitives
BUFGCTRL
The BUFGCTRL primitive shown in
clocks. All other global clock buffer primitives are derived from certain configurations of
BUFGCTRL. The ISE® software tools manage the configuration of all these primitives.
BUFGCTRL has four select lines, S0, S1, CE0, and CE1. It also has two additional control
lines, IGNORE0 and IGNORE1. These six control lines are used to control the input I0 and
I1.
BUFGCTRL is designed to switch between two clock inputs without the possibility of a
glitch. When the presently selected clock transitions from High to Low after S0 and S1
Notes:
1. All primitives are derived from a software preset of BUFGCTRL.
BUFGCTRL
BUFG
BUFGCE
BUFGCE_1
BUFGMUX
BUFGMUX_1
BUFGMUX_VIRTEX4
Primitive
Table 1-3
www.xilinx.com
Input
I0, I1
I0, I1
I0, I1
I0, I1
Figure 1-1: BUFGCTRL Primitive
are different configurations of the global clock buffers.
I
I
I
IGNORE1
CE1
S1
I1
I0
S0
CE0
IGNORE0
Output
Figure
O
O
O
O
O
O
O
BUFGCTRL
CE0, CE1, IGNORE0, IGNORE1, S0, S1
–
CE
CE
S
S
S
1-1, can switch between two asynchronous
UG070_1_01_031208
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UG070 (v2.6) December 1, 2008
Control
Virtex-4 FPGA User Guide
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