XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 159

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Case 2: Writing to a Full or Almost Full FIFO
For the example in
event 2 is with respect to write-clock, while clock event 4 is with respect to read-clock.
Clock event 4 appears three read-clock cycles after clock event 2.
•
•
•
•
If the rising WRCLK edge is close to the rising RDCLK edge, AEMPTY could be deasserted
one RDCLK period later.
Prior to the operations performed in
example, the timing diagram reflects of both standard and FWFT modes.
Clock Event 1: Write Operation and Assertion of ALMOSTFULL Signal
During a write operation to an almost full FIFO, the ALMOSTFULL signal is asserted.
•
•
•
WRERR
WRCLK
RDCLK
AFULL
WREN
RDEN
FULL
At time T
inputs of the FIFO.
Write enable remains asserted at the WREN input of the FIFO.
At clock event 4, DO output pins of the FIFO remains at 00 since no read has been
performed. In the case of standard mode, data 00 will never appear at the DO output
pins of the FIFO.
At time T
at the AEMPTY pin. In the case of standard mode, AEMPTY deasserts in the same
way as in FWFT mode.
At time T
inputs of the FIFO.
At time T
the WREN input of the FIFO.
At time T
asserted at the AFULL output pin of the FIFO.
DI
FDCK_DI
FCKO_AEMPTY
FDCK_DI
FCCK_WREN
FCKO_AFULL
Figure
Figure 4-18: Writing to a Full / Almost Full FIFO
1
, before clock event 2 (WRCLK), data 03 becomes valid at the DI
, before clock event 1 (WRCLK), data 00 becomes valid at the DI
00
, before clock event 1 (WRCLK), write enable becomes valid at
, one clock cycle after clock event 1 (WRCLK), ALMOSTFULL is
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4-17, the timing diagram is drawn to reflect FWFT mode. Clock
T
T
, after clock event 4 (RDCLK), ALMOSTEMPTY is deasserted
FCCK_WREN
FDCK_DI
01
Figure
T
FCKO_FULL
02
4-18, the FIFO is almost completely full. In this
T
FDCK_DI
FIFO Timing Models and Parameters
03
T
T
FCKO_WERR
FCKO_FULL
2
04
T
FCCK_WREN
T
FCKO_WERR
3
05
ug070_4_18_071204
T
FDCK_DI
4
06
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