XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 74

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 2: Digital Clock Managers (DCMs)
74
Characteristics of the Deskew Circuit
Cascading DCMs
In some situations, the DCM does not add this extra delay, and the DESKEW_ADJUST
parameter has no effect. BitGen selects the appropriate DCM tap settings. These situations
include:
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•
•
Source-Synchronous Setting
When DESKEW_ADJUST is set to source-synchronous mode, the DCM feedback delay
element is set to zero. As shown in
clock feedback delay element is set to minimize the sampling window. This results in a
more positive hold time and a longer clock-to-out compared to system-synchronous mode.
The source-synchronous switching characteristics section in the
the various timing parameters for the source-synchronous design when the DCM is in
source-synchronous mode.
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•
•
•
•
•
•
Xilinx does not recommend cascading DCMs because jitter accumulates as a result—in
other words, the output clock jitter of the second-stage DCM is worse than the output clock
jitter of the first-stage DCM. If possible, use two DCMs in parallel instead of in series.
If it is absolutely necessary to cascade DCMs, the following rules must be observed:
•
•
•
downstream DCMs when two or more DCMs are cascaded
DCMs with external feedback
DCMs with an external CLKIN that does not come from a dedicated clock input pin
Eliminate clock distribution delay by effectively adding one clock period delay.
Clocks are deskewed to within CLKOUT_PHASE, specified in the
Eliminate on-chip as well as off-chip clock delay.
No restrictions on the delay in the feedback clock path.
Requires a continuously running input clock.
Adapts to a wide range of frequencies. However, once locked to a frequency, large
input frequency variations are not tolerated.
Does not eliminate jitter. The deskew circuit output jitter is the accumulation of input
jitter and any added jitter value due to the deskew circuit.
The completion of configuration can be delayed until after DCM locks to guarantee
the system clock is established prior to initiating the device.
The output jitter specifications for DLL outputs are provided in the data sheet. Use the
Jitter Calculator to determine the jitter for CLKFX. If possible, avoid cascading CLKFX
to CLKFX in high-frequency mode. In general, jitter accumulates based on the
following equation:
The input and output frequency and jitter specifications for each DCM must be met. If
the frequency of the DCM inputs allows it, use feedback for both DCMs.
Use the LOCKED output from DCM1 to create a Reset for DCM2. The recommended
length of a Reset pulse is 200ms. The LOCKED signal from DCM1 should be inverted
and provide the Reset input to DCM2. Connect the output of DCM1 to CLKIN of
DCM2 through a BUFGCTRL. CLKIN and the DCM output clock (CLKDV in this
case) feed a BUFGCTRL acting as an asynchronous mux. When DCM1 is in reset and
Total Jitter
www.xilinx.com
Figure
=
(
2-4, in source-synchronous mode, the DCM
Jitter1
)
2
+
(
Jitter2
UG070 (v2.6) December 1, 2008
Virtex-4 Data Sheet
)
2
Virtex-4 FPGA User Guide
Virtex-4 Data
reflects
Sheet.
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