XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 370

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Advanced SelectIO Logic Resources
370
Divided Clock Input – CLKDIV
Serial Input Data from IOB – D
High-Speed Clock for Strobe-Based Memory Interfaces – OCLK
Reset Input – SR
The divided clock input (CLKDIV) is typically a divided version of CLK (depending on the
width of the implemented deserialization). It drives the output of the serial-to-parallel
converter, the delay element, the Bitslip submodule, and the CE module.
The serial input data port (D) is the serial (high-speed) data input port of the ISERDES.
This port works in conjunction with all the Virtex-4 FPGA I/O resources to accommodate
the desired I/O standards.
The OCLK clock input is used to transfer strobe-based memory data onto a free-running
clock domain. OCLK is a free-running FPGA clock at the same frequency as the strobe on
the CLK input. The domain transfer from CLK to OCLK is shown in the block diagram of
Figure
of the strobe signal to the CLK input (e.g., using IDELAY). Examples of setting the timing
of this domain transfer are given in several memory-related application notes, including
XAPP721
this port is unused and should be grounded.
The reset input causes the outputs of all data flip-flops in the CLK and CLKDIV domains
to be driven LOW asynchronously. For circuits in the ISERDES running on the CLK
domain where timing is critical, there is an internal, dedicated circuit to re-time the SR
input to produce a reset signal synchronous to the CLK domain. Similarly, there is also a
dedicated circuit to re-time the SR input to produce a reset signal synchronous to the
CLKDIV domain. Because there are circuits in the ISERDES that re-time the SR input, the
user is only required to provide a reset pulse to the SR input that meets timing on the
CLKDIV frequency domain. Therefore, SR should be driven High for a minimum of one
CLKDIV cycle.
When building an interface consisting of multiple ISERDES, it may be important that all
ISERDES in the interface are synchronized to one another. The internal re-timing of the SR
input guarantees that all ISERDES that receive the same reset pulse come out of reset in
sync with one another. The reset timing of multiple ISERDES is shown in
page
Clock Event 1
A reset pulse is generated on the rising edge of CLKDIV. Because the pulse must take two
different routes to get to ISERDES0 and ISERDES1, there are different propagation delays
for both paths. The difference in propagation delay is emphasized in
to ISERDES0 is very long and the path to ISERDES 1 is very short, such that each ISERDES
receives the reset pulse in a different CLK cycle. The internal resets for both CLK and
CLKDIV go into reset asynchronously when the SR input is asserted.
371.
8-6. The timing of the domain transfer must be set by the user by adjusting the delay
(available on www.xilinx.com). When INTERFACE_TYPE is NETWORKING,
www.xilinx.com
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
Figure
Figure 8-5,
8-5. The path
R