XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 368

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Advanced SelectIO Logic Resources
Table 8-1: ISERDES Port List and Definitions (Continued)
368
DLYCE
DLYINC
DLYRST
OCLK
REV
SHIFTIN1
SHIFTIN2
SR
Port Name
ISERDES Ports
Input
Input
Input
Input
Input
Input
Input
Input
Type
Combinatorial Output – O
Registered Outputs – Q1 to Q6
Bitslip Operation – BITSLIP
The combinatorial output port (O) is an unregistered output of the ISERDES module. This
output can come directly from the data input (D), or from the data input (D) via the
IDELAY block.
The output ports Q1 to Q6 are the registered outputs of the ISERDES module. The outputs
are synchronous to CLKDIV. The first bit clocked into the ISERDES are clocked out on Qn,
where n is the width of the deserialization. One ISERDES block can support up to six bits
(i.e., a 1:6 deserialization). Bit widths greater than 6 (up to 10) can be supported (see
“ISERDES Width
The bit ordering at the input of an OSERDES is the opposite of the bit ordering at the
output of an ISERDES, as shown in
bit “A” of the word “FEDCBA” is placed at the D1 input of an OSERDES, but the same bit
“A” emerges from the ISERDES at the Q6 output. In other words, D1 is the least significant
input to the OSERDES, while Q6 is the least significant output of the ISERDES. When
width expansion is used, D1 of the master OSERDES is the least significant input, while Q6
of the slave ISERDES is the least significant output.
The BITSLIP pin performs a Bitslip operation synchronous to CLKDIV when asserted
(active High). Subsequently, the data seen on the Q1 to Q6 output ports shift, as in a barrel-
shifter operation, one position every time Bitslip is invoked. The nature of the shift differs
for SDR and DDR modes. See
Width
1
1
1
1
1
1
1
1
Enable IDELAY increment/decrement function. The DLYCE port is the same as
the CE port in the IDELAY primitive. See
Increment/decrement number of tap delays in IDELAY. The DLYINC port is the
same as the INC port in the IDELAY primitive. See
Reset IDELAY to pre-programmed value. If no value programmed, reset to 0. The
DLYRST port is the same as the RST port in the IDELAY primitive. See
Ports”.
High-speed clock input for memory applications.
Reverse SR pin. Not available in the ISERDES block; connect to GND.
Carry input for data width expansion. Connect to SHIFTOUT1 of master IOB. See
“ISERDES Width
Carry input for data width expansion. Connect to SHIFTOUT2 of master IOB. See
“ISERDES Width
Active High reset. See
Expansion”).
www.xilinx.com
Expansion”.
Expansion”.
“BITSLIP Submodule”
“Reset Input – SR”
Figure 8-3, page
Description
“IDELAY
in section “ISERDES Ports.”
369. For example, the least significant
for more details.
UG070 (v2.6) December 1, 2008
“IDELAY
Ports”.
Virtex-4 FPGA User Guide
Ports”.
“IDELAY
R