XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 107

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
IBUFG, BUFG, and PMCD
R
•
•
When deskewed clocks are not required, a PMCD can be used without a DCM.
and
Reset
The REL signals of the parallel PMCDs must be driven directly from the DCM
LOCKED output.
♦
To match output skews between two PMCDs, a DCM must connect to two PMCDs in
the same tile (group of two).
Figure 3-10
GCLK
IOB
to the corresponding DCM feedback clock ensures all PMCD outputs will start
synchronously. Note: CLK2X feedback is not supported.
Dedicated, timing-matched routes for both CLK signals and LOCKED signals
exist from the DCMs to the PMCDs on the same top/bottom half of the device.
CLKIN
CLKFB
RST
illustrate these examples.
DCM
Figure 3-9:
LOCKED
CLK180
Figure 3-8: DCM and Parallel PMCDs
CLK0
www.xilinx.com
PMCD Driven by IBUFG (GCLK IOB)
Reset
Reset
Reset
RST_DEASSERT_CLK = CLKA
EN_REL = FALSE
CLKA
RST
REL
RST_DEASSERT_CLK = CLKB
EN_REL = TRUE
RST_DEASSERT_CLK = CLKA
EN_REL = TRUE
CLKA
CLKB
RST
REL
CLKA
RST
REL
PMCD
PMCD #1
PMCD #2
CLKA1D2
CLKA1D4
CLKA1D8
CLKA1D2
CLKA1D4
CLKA1D8
CLKA1D2
CLKA1D4
CLKA1D8
CLKA1
CLKA1
CLKA1
Application Examples
UG070_3_09_071404
UG070_3_08_071404
BUFGs
BUFGs
Figure 3-9
107