XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 379

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
ISERDES Latencies
ISERDES Timing Model and Parameters
R
When the ISERDES interface type is MEMORY, the latency through the OCLK stage is
1 CLKDIV cycle. However the total latency through the ISERDES depends on the phase
relationship between the CLK and the OCLK clock inputs. When it is NETWORKING, the
latency is 2 CLKDIV cycles. See
visualization of latency in networking mode. The extra CLKDIV cycle of latency in
NETWORKING mode (compared to MEMORY mode) is due to the Bitslip submodule.
Table 8-5
characteristics in the
Table 8-5: ISERDES Switching Characteristics
Setup/Hold for Control Lines
Setup/Hold for Data Lines
Sequential Delay
T
T
T
T
T
T
T
T
T
T
ISCCK_SR_SYNC
ISCCK_BITSLIP
ISCCK_CE
ISCCK_CE
ISCCK_DLYCE
ISCCK_DLYINC
ISCCK_DLYRST
ISDCK_D
ISDCK_DDR
ISCKO_Q
describes the function and control signals of the ISERDES switching
/ T
/T
/T
Symbol
/ T
ISCKD_D
ISCKC_CE
ISCKC_CE
/ T
/ T
/ T
/ T
ISCKD_DDR
/ T
ISCKC_DLYCE
ISCKC_BITSLIP
ISCKC_DLYRST
Virtex-4 Data
ISCKC_DLYINC
ISCKC_SR_SYNC
www.xilinx.com
Figure 8-12, page 385
Sheet.
Input Serial-to-Parallel Logic Resources (ISERDES)
SR Pin setup/hold with respect to CLKDIV
BITSLIP pin setup/hold with respect to CLKDIV
CE pin setup/hold with respect to CLK (for CE1)
CE pin setup/hold with respect to CLKDIV (for CE2)
DLYCE pin setup/hold with respect to CLKDIV
DLYINC pin setup/hold with respect to CLKDIV
DLYRST pin setup/hold with respect to CLKDIV
D pin setup/hold with respect to CLK
(IOBDELAY = IBUF or NONE)
D pin setup/hold with respect to CLK
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = DEFAULT)
D pin setup/hold with respect to CLK
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = FIXED,
IOBDELAY_VALUE = 0)
D pin setup/hold with respect to CLK at DDR mode
(IOBDELAY = IBUF or NONE)
D pin setup/hold with respect to CLK at DDR mode
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = DEFAULT)
D pin setup/hold with respect to CLK at DDR mode
(IOBDELAY = IFD or BOTH,
IOBDELAY_TYPE = FIXED,
IOBDELAY_VALUE = 0)
CLKDIV to Out at Q pins
and
Description
Figure 8-13, page 385
for a
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