XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 337

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Verilog for Zero-Hold Time Delay Mode
Fixed Delay Mode
The following code shows how to instantiate the IDELAY module in fixed delay mode
with a tap setting of 31. IDELAYCTRL must also be instantiated when operating in this
mode (see
-- Architecture Section
--
attribute IOBDELAY_TYPE : string;
attribute IOBDELAY_VALUE: integer;
-- Component Instantiation for IDELAY should be placed
-- in architecture after the "begin" keyword
--
-- Instantiation Section
--
U1 : IDELAY
generic map (
port map (
// Module: IDELAY
// Description: Verilog instantiation template
// Zero Hold Time Mode
//
// Device: Virtex-4 Family
//-------------------------------------------------------------------
// Instantiation Section
//
IDELAY U1
//Set IOBDELAY_TYPE attribute to DEFAULT for Zero Hold Time Mode
//synthesis attribute IOBDELAY_TYPE of U1 is "DEFAULT";
//synthesis attribute IOBDELAY_VALUE of U1 is 0;
(
);
“IDELAYCTRL Overview,” page
O(data_output)
I(data_input),
C(1’b0),
CE(1’b0),
INC(1’b0),
RST(1’b0)
);
O => data_output,
I => data_input,
C => ’0’,
CE => ’0’,
INC => ’0’,
RST => ’0’
);
IOBDELAY_TYPE => "DEFAULT", -- Set to DEFAULT for
IOBDELAY_VALUE => 0
www.xilinx.com
341).
-- (0 to 63)
-- Zero Hold Time Mode
ILOGIC Resources
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