XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 251

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Virtex-4 FPGA I/O Resource VHDL/Verilog Examples
R
PULLUP/PULLDOWN/KEEPER for IBUF, OBUFT, and IOBUF
Differential Termination Attribute
VHDL Template
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The CAPACITANCE attribute uses the following syntax in the UCF file:
When using 3-state output (OBUFT) or bidirectional (IOBUF) buffers, the output can have
a weak pull-up, a weak pull-down, or a weak keeper circuit. For input (IBUF) buffers, the
input can have either a weak pull-up or a weak pull-down circuit. These features can be
invoked by adding one of the following possible constraint values to the buffer:
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Xilinx recommends that these internal termination circuits (weak pull-ups, weak pull-
downs and weak keepers) not be used to hold a logic level for a 3-stated signal. It is highly
likely that coupled noise from a PCB trace would swamp out the effect of these termination
circuits. The intended application of the internal termination circuits is to hold logic values
for unconnected pins to prevent spurious switching and consequent power loss. Internal
termination circuits are not intended to drive board-level traces to a defined logic level.
The differential termination (DIFF_TERM) attribute is designed for the Virtex-4 FPGA
supported differential input I/O standards. It is used to turn the built-in 100Ω differential
termination on or off.
The allowed values for the DIFF_TERM attribute are:
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•
To specify the DIFF_TERM attribute, set the appropriate value in the generic map (VHDL)
or inline parameter (Verilog) of the instantiated IBUFDS or IBUFGDS component. Please
refer to the ISE® software Language Templates or the Virtex-4 FPGA HDL Libraries Guide
for the proper syntax for instantiating this component and setting the DIFF_TERM
attribute.
The following examples are VHDL and Verilog syntaxes to declare a standard for Virtex-4
FPGA I/O resources. The example uses IOBUF.
NORMAL
LOW
INST <I/O_BUFFER_INSTANTIATION_NAME> CAPACITANCE=
"<CAPACITANCE_VALUE>";
PULLUP
PULLDOWN
KEEPER
TRUE
FALSE (Default)
--Example IOBUF component declaration
component IOBUF
generic(
CAPACITANCE : string
DRIVE
IOSTANDARD
www.xilinx.com
: integer
: string
:= "DONT_CARE";
:= 12;
:= "LVCMOS25";
Virtex-4 FPGA SelectIO Primitives
251