XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 167

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
RDCLK Faster than WRCLK Design
User-Programmable Flag Settings in the Composite FIFO
In this case (shown in
WRCLKLUTFIFO. The RDCLKLUTFIFO and WRCLKFIFO16 are driven from RDCLKbar,
which is a 180-degree phase-shifted version of RDCLK. The RDCLK of the FIFO is
connected to RDCLKFIFO16. The LUTFIFO forms the write interface of the composite
FIFO; its read side is clocked by the inverted read clock, which is also used to write into the
FIFO16. LUTFIFO flags are combined and synchronized to the write clock to generate the
ALMOSTFULL flag.
The offset ranges for user-programmable ALMOSTEMPTY and ALMOSTFULL flags
along with the FIFO capacity are listed in
normally not critical, most applications use the ALMOSTFULL flag not only as a warning
but also as a signal to stop writing. The ALMOSTEMPTY flag can be used as a warning
that the FIFO is approaching EMPTY, but to ensure that the very last entries in the FIFO are
read out, reading should be continued until EMPTY is asserted.
When setting the offset ranges in the provided Perl script (refer to Design Files below), use
decimal notation.
Table 4-15: FIFO Capacity and Effective ALMOSTFULL/ALMOSTEMPTY Flag Offsets
All values can vary by up to 3 words, depending on the read/write clock rates and the
read/write patterns.
Notes:
1. FIFO16 = Capacity of FIFO16. Refer to
2. AF
3. AE
ALMOST
ALMOST_FULL_OFFSET
ALMOST_EMPTY_OFFSET
WRERR
WRCLK
WREN
DI/DIP
FULL
FULL
FIFO16
FIFO16
= Set by user in Perl script. Sets the FIFO16 ALMOST_FULL_OFFSET. Refer to
= Set by user in Perl script. Sets the FIFO16 ALMOST_EMPTY_OFFSET. Refer to
FIFO Depth
Clock Style
FIFO Type
wdat
wrclk
full
overflow
LUTFIFO
Figure 4-26: RDCLK Faster than WRCLK Design
Figure
empty
www.xilinx.com
rdclk
rden
rdat
4-26), the WRCLK of the FIFO is connected to
RDCLKbar
Table
4-9,
Table
WRCLK > RDCLK
FIFO16 Error Condition and Work-Arounds
AE
AF
“FIFO Capacity.”
FIFO16
FIFO16
4-15. Since the full capacity of any FIFO is
WRCLK
(2)
(3)
+ 15
+ 15
Standard/FWFT
FIFO16
wdat
afull
wren
wrclk
Optional FWFT
FIFO16
(1)
aempty
+ 15
RDCLK > WRCLK
empty
rdclk
rderr
rden
rdat
AE
FIFO16
15
UG070_c4_27_031208
Table
Table
(3)
DO/DOP
RDEN
RDCLK
ALMOST
EMPTY
EMPTY
RDERR
4-13.
4-13.
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