XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 382

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 8: Advanced SelectIO Logic Resources
382
ISERDES Verilog Instantiation
port map (
// Module: ISERDES
// Description: Verilog instantiation template
//
// Device: Virtex-4 Family
//-------------------------------------------------------------------
// Instantiation Section
//
ISERDES U1
(
.O (data_output),
.Q1 (Q[0]),
.Q2 (Q[1]),
.Q3 (Q[2]),
.Q4 (Q[3]),
.Q5 (open),
.Q6 (open),
.SHIFTOUT1 (open),
.SHIFTOUT2 (open),
.BITSLIP (bitslip),
.CE1 (ce),
);
O => data_output,
Q1 => Q(0),
Q2 => Q(1),
Q3 => Q(2),
Q4 => Q(3),
Q5 => open,
Q6 => open,
SHIFTOUT1 => open,
SHIFTOUT2 => open,
BITSLIP => bitslip,
CE1 => ce,
CE2 => open,
CLK => clk
CLKDIV => clkdiv
D => data_input
DLYCE => dlyce,
DLYINC => dlyinc,
DLYRST => dlyrst,
OCLK => open,
REV => open,
SHIFTIN1 => open,
SHIFTIN2 => open,
SR => rst,
BITSLIP_ENABLE => "FALSE", --(TRUE, FALSE)
DATA_RATE => "DDR", --(SDR, DDR)
DATA_WIDTH => 4, --(2,3,4,5,6,7,8,10)
INTERFACE_TYPE => "MEMORY", --(MEMORY, NETWORKING)
IOBDELAY => "NONE", --(NONE,IBUF,IFD,BOTH)
IOBDELAY_TYPE => "DEFAULT", --(DEFAULT, FIXED, VARIABLE)
IOBDELAY_VALUE => 0, --(0 to 63)
NUM_CE => 2, --(1,2)
SERDES_MODE => "MASTER", --(MASTER, SLAVE)
);
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Virtex-4 FPGA User Guide
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