XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 125

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Table 4-2: Port Aspect Ratio
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Port Data Width
18
36
1
2
4
9
Write Enable - WE[A|B]
Register Enable - REGCE[A|B]
Set/Reset - SSR[A|B]
Address Bus - ADDR[A|B]<14:#>
Data-In Buses - DI[A|B]<#:0> & DIP[A|B]<#:0>
R
Port Address Width
To write the content of the data input bus into the addressed memory location, both EN
and WE must be active within a setup time before the active clock edge. The output latches
are loaded or not loaded according to the write configuration (WRITE_FIRST,
READ_FIRST, NO_CHANGE). When inactive, a read operation occurs, and the contents of
the memory cells referenced by the address bus reflect on the data-out bus, regardless of
the write mode attribute. Write enable polarity is configurable (active High by default).
The register enable pin (REGCE) controls the optional output register. When the RAM is in
register mode, REGCE = 1 registers the output into a register at a clock edge. The polarity
of REGCE is configurable (active High by default).
The SSR pin forces the data output latches to contain the value “SRVAL” (see
Attributes,” page
including the parity bit. In a 36-bit width configuration, each port has an independent
SRVAL[A|B] attribute of 36 bits. This operation does not affect RAM cells and does not
disturb write operations on the other port. Similar to the read and write operation, the
set/reset function is active only when the enable pin of the port is active. Set/reset polarity
is configurable (active High by default). This pin is not available when optional output
registers are used.
The address bus selects the memory cells for read or write. The width of the port
determines the required address bus width for a single RAMB16, as shown in
For cascadable block RAM, the data width is one bit, however, the address bus is 15 bits
<14:0>. The address bit 15 is only used in cascadable block RAM.
Data and address pin mapping is further described in the
Design
Data-in buses provide the new data value to be written into RAM. The regular data-in bus
(DI), and the parity data-in bus (DIP) when available, have a total width equal to the port
14
13
12
11
10
9
Considerations”section.
127). The data output latches are synchronously asserted to 0 or 1,
Depth
16,384
8,192
4,096
2,048
1,024
512
www.xilinx.com
ADDR Bus
<13:0>
<13:1>
<13:2>
<13:3>
<13:4>
<13:5>
DI Bus / DO Bus
<15:0>
<31:0>
<1:0>
<3:0>
<7:0>
<0>
“Additional RAMB16 Primitive
Block RAM Port Signals
DIP Bus / DOP Bus
<1:0>
<3:0>
<0>
NA
NA
NA
“Block RAM
Table
4-2.
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