XC4VFX40-10FFG1152C Xilinx Inc, XC4VFX40-10FFG1152C Datasheet - Page 146

• Manufacturer Part Number: XC4VFX40-10FFG1152C
• Description: IC FPGA VIRTEX-4 FX 40K 1152FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX40-10FFG1152C

• Number Of Logic Elements/cells: 41904
• Number Of Labs/clbs: 4656
• Total Ram Bits: 2654208
• Number Of I /o: 448
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 4: Block RAM
146
Block RAM Timing Model
Clock Event 4
Clock Event 5
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SSR (Synchronous Set/Reset) Operation
During an SSR operation, initialization parameter value SRVAL is loaded into the output
latches of the block RAM. The SSR operation does NOT change the contents of the memory
and is independent of the ADDR and DI inputs.
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•
Disable Operation
Deasserting the enable signal EN disables any write, read, or SSR operation. The disable
operation does NOT change the contents of the memory or the values of the output latches.
•
•
Figure 4-13
This example takes the simplest paths on and off chip (these paths can vary greatly
depending on the design). This timing model demonstrates how and where the block
RAM timing parameters are used.
•
•
•
•
At time T
following the block RAM.
At time T
the block RAM.
At time T
valid (High) at the SSR input of the block RAM.
At time T
outputs of the block RAM.
At time T
EN input of the block RAM.
After clock event 5, the data on the DO outputs of the block RAM is unchanged.
NET = Varying interconnect delays
T
T
T
IOPI
IOOP
BCCKO_O
= Pad to I-output of IOB delay
= O-input of IOB to pad delay
illustrates the delay paths associated with the implementation of block RAM.
RCCK_WEN
RCKO_DO
RCCK_SSR
RCKO_DO
RCCK_EN
= BUFGCTRL delay
before clock event 5, the enable signal becomes valid (Low) at the
after clock event 2, data CCCC becomes valid at the DO outputs of
after clock event 4, the SRVAL 0101 becomes valid at the DO
before clock event 4, the synchronous set/reset signal becomes
before clock event 2, write enable becomes valid at the WEN
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UG070 (v2.6) December 1, 2008
Virtex-4 FPGA User Guide
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