TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 19

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

Pin Functions and Initial Values Arranged by Type of Power Supply – 2 (DVCCM)
Pin Functions and Initial Values Arranged by Type of Power Supply – 3 (DVCC3IO)
Power supply to
Power supply
to be used
DVCC3IO
DVCCM
be used
Note 2: When the “Input buffer” column shows “ON”, the pin is enabled as an input in the initial state. If necessary,
Note 1: Pin names "SA0 through SA7, …, and SR0 through SR4" are symbols used for convenience and are
Typical pin name
Typical pin name
Note 1: Pin names "SA0 through SA7, …, and SR0 through SR4" are symbols used for convenience and are
Note 2: When the “Input buffer” column shows “ON”, the pin is enabled as an input in the initial state. If necessary,
SM2
SM3
SM4
SM6
SM7
SN0
SN1
SN2
SP0
SP1
SP2
SP3
SP4
SP5
SL0
SL1
SL2
SL4
SL5
SL6
different from general-purpose port functions "PA0 through PA7, …, and PV0 through PV7."
the pin should be processed externally. The data bus pins for NAND Flash memory (NDD0-NDD7) are
disabled as inputs in the initial state.
different from general-purpose port functions "PA0 through PA7, …, and PV0 through PV7."
the pin should be processed externally. When DDR SDRAM is used, the DQS signals (DMCDDQS0,
DMCDDQS1) are always enabled as inputs. These pins must be tied externally (pulled up/down, etc.) to
prevent flow-through current.
DMCDDQS0
DMCDDQS1
DMCDCLKN
SELDVCCM
DMCCLKIN
DMCSCLK
SELMEMC
Alternative
Alternative
SELJTAG
RESETn
DMCAP
function
function
TRSTn
RTCK
TDO
AM0
AM1
TCK
TMS
XT1
XT2
TDI
TMPA901CM- 18
DMCDCLKP
Alternative
Alternative
function
function
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
up/down
up/down
Pull
Pull
PU
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
－
buffer
buffer
Input
Input
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
－
－
－
－
－
－
－
When SELMEMC
When SELMEMC
When SELMEMC
When SELMEMC
output
TDO out / TDO output
DMCAP out / “L” output
DMCDDQS0 / Hz*
DMCDDQS1 / Hz*
DMCCLKIN input / Hz
Oscillating
Oscillating
RESETn input / “H” output
AM0 input / Hz
AM1 input / Hz
SELMEMC input / Hz
SELDVCCM input / Hz
SELJTAG input / Hz
TCK input / Hz
TMS input/ Hz
TDI input / Hz
TRSTn input / Hz
RTCK out / CLK output
DMCSCLK out / CLK output
DMCDCLKP out / CLK output
Invalid signal/ “H” output
DMCDCLKN out / Inverted CLK
Initial value after reset
Initial state after reset
function/pin state
function/pin state
TMPA901CM
0
1
0
1
2010-07-29