TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 92

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

12. VICVECTPRIORITY0 (Vector Priority 0 Register)
13. VICADDRESS (Vector Address Register)
[31:4]
[3:0]
[31:0]
[Description]
[Description]
a. <VectPriority>
a. <VectAddr>
Bit
Bit
This register can be read current active address of Interrupt Service Routine.
And current interruption can be clear.
If multiple interrupt requests of the same software priority level occur simultaneously, the
hardware priority is used to determine the interrupt to be generated.
The hardware priority is assigned according to interrupt source numbers: interrupt source
number 0 has the highest priority and interrupt source number 31 has the lowest priority.
Read: return the address of the currently active Interrupt Service Routine (ISR.)
Write: Writing any data to this register clears the current interrupt.
Note:
VICVECTPRIORITYn (Vector Priority n Register)(n = 0 to 6, 8, 10 to12, 14, 16 to 18, 20,
21,23, 27, 30, 31)
This register can be set the software priority level of
0y0000 is highest level, and can set 16 level (0y0000 to 0y1111).
The structure and description of these registers are same as VICVECTPRIORITY0.
Please refer to the description of VICVECTPRIORITY0.
The name and address of these registers, please refer to Table 3.7.2.
A read of this register must only be performed when there is an active interrupt.
A write of this register must only be performed at the end of an ISR.
VectPriority
VectAddr
Symbol
Symbol
Bit
Bit
R/W
R/W
Type
Type
TMPA901CM- 91
Undefined
0y1111
0x00000000
Reset
Value
Reset
Value
Address of the currently active Interrupt
Service Routine (ISR)
Read as undefined. Write as zero.
S/W Priority level for interrupt source
0: 0y0000 to 0y1111
Address
Address
IRQ.
Description
(0xF400_0000) + (0x0200)
(0xF400_0000) + (0x0F00)
Description
TMPA901CM
2010-07-29