TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 442

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:30]
[29]
[28:26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16:11]
[10]
[9]
[8]
Bit
int_mw_rerror
int_dmac_reg_rd
int_udc2_reg_rd
int_mr_ahberr
int_mr_ep_dset
int_mr_end_add
int_mw_ahberr
int_mw_timeout
int_mw_end_add
int_mw_set_add
int_usb_reset_end
int_usb_reset
int_suspend_resume
Note: For the operation of interrupt signals, refer to “3.16.2.7 Interrupt Signal (INTS[21])”.
1. UDINTSTS (Interrupt Status register)
Symbol
status can be cleared by writing 1 into bits [29:8]. Bits [7:0] corresponds to the output
pins of UDC2 and read-only. It can be cleared by writing 1 into the appropriate bit of
INT register in UDC2.
Bit
This register sets 1 to each corresponding bit when an interrupt source arises. The
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
R/W1C
Type
Undefined
0y0
Undefined
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
0y0
Undefined
0y0
0y0
0y0
Reset
Value
TMPA901CM- 441
Read as undefined. Write as zero.
Master Write Endpoint Read error
0y0: Not detected
0y1: Endpoint read error occurred in Master Write
Read as undefined. Write as zero.
DMAC register access complete
0y0: Not detected
0y1: Register read completed
UDC2 register access complete
0y0: Not detected
0y1: Register read/write completed
Master Read transfer error status
0y0: Not detected
0y1: AHB error occurred
Master Read endpoint data set status
0y0: FIFO is not writable
0y1: FIFO is writable
Master Read transfer end status
0y0: Not detected
0y1: Master Read transfer finished
Master Write transfer error status
0y0: Not detected
0y1: AHB error occurred
Master Write transfer time-out status
0y0: Not detected
0y1: Master Write transfer timed out
Master Write transfer end status
0y0: Not detected
0y1: Master Write transfer finished
Master Write transfer address request status
0y0: Not detected
0y1: Master Write transfer address request
Read as undefined. Write as zero.
USB_RESET END
0y0: UDC2 has not deasserted the usb_reset signal after this
bit was cleared.
0y1: Indicates UDC2 has deasserted the usb_reset signal.
USB_RESET
0y0: UDC2 has not asserted the usb_reset signal after this bit
was cleared.
0y1: Indicates UDC2 has asserted the usb_reset signal.
Suspend/resume interrupt status
0y0: Status has not changed
0y1: Status has changed
Description
Address = (0xF440_0000) + (0x0000)
TMPA901CM
2010-07-29