TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 333

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

3.13.1.1 Operation Description
Note:The number of STOP bit can be selected as 1 bit or 2 bits by setting UARTxLCR_H<STP2>. The term STOP bit
(1) Baud rate generator
(2) Transmit FIFO
(3) Receive FIFO
(4) Transmit logic
(5) Receive logic
(6) Interrupt generation logic
(7) Interrupt timing
here means the last STOP bit.
The transmit FIFO is an 8-bit wide, 16-location deep, FIFO memory buffer. CPU data
written across the APB interface is stored in the FIFO until it is read out by the
transmit logic. You can disable the transmit FIFO to act like a one-byte holding
register.
The receive FIFO is a 12-bit wide, 16 locations deep, FIFO memory buffer. Received
data and corresponding error bits are stored in the receive FIFO by the receive logic
until they are read out by the CPU across the APB interface. The receive FIFO can be
disabled to act like a one-byte holding register.
The transmit logic performs parallel-to-serial conversion on the data read from the
transmit FIFO. Control logic outputs the serial bit stream beginning with a start bit,
data bits with the Least Significant Bit (LSB) first, followed by the parity bit, and then
the stop bits according to the programmed configuration in control registers.
The receive logic performs serial-to-parallel conversion on the received bit stream after
a start bit has been detected. Error check for overrun, parity and frame and line break
detection are also performed. Their error bit data is written to the receive FIFO.
timing of UART transmit and receive, and the internal IrLPBaud16 circuit which
generates the pulse width of the IrDA encoded transmit bit stream when in low-power
mode.
UART outputs a maskable combined interrupt for every interrupt sources.
The baud rate generator contains the internal Baud16 clock circuit which controls the
Overrun error
Break error
Parity error
Frame error
Receive timeout error
Transmit interrupt
Receive interrupt
Interrupt type
After receiving the stop bit of Overflow data
After receiving STOP bit
After receiving parity data
After receiving frame over bit
After 511 clocks (Baud16) from Receive FIFO data storage.
After transmitting the last data (MSB data).
After receiving STOP bit
TMPA901CM- 332
Interrupt timing
TMPA901CM
2010-07-29