TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 386

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:8]
[7]
[6]
[5]
[4]
[3]
[2]
[1:0]
[Description]
a. <MST>
b. <TRX>
c. <BB>
Bit
Note: Refer to Section 3.14.6.3 “Serial CLock”.
Note: Refer to Section 3.14.6.3 “Serial Clock”.
Note: Refer to Section 3.14.6.3 “Serial Clock”.
4.
This bit selects master or slave mode.
0y0: Slave
0y1: Master
This bit selects transmission or reception mode.
0y0: Reception
0y1: Transmission
This bit is used to generate a start or stop condition.
0y0: Generate a stop condition.
0y1: Generate a start condition.
I2C0CR2 (I
MST
TRX
BB
PIN
I2CM
SWRES[1:0]
Bit Symbol
2
C0 Control Register 2) (Write Only)
WO
WO
WO
WO
WO
WO
Type
TMPA901CM- 385
Undefined
0y0
0y0
0y0
0y1
0y0
Undefined
0y00
Reset
Value
Read as undefined. Write as zero.
Selects master or slave mode.
0y0: Slave
0y1: Master
Selects transmit or receive operation.
0y0: Receiver
0y1: Transmitter
Selects whether to generate a start or stop
condition.
0y0: Generate a stop condition.
0y1: Generate a start condition.
Service request clear
0y0: No effect
0y1: Clear service request
I
0y0: Disable
0y1: Enable
Read as undefined. Write as zero.
Software reset
A software reset is generated by writing 0y10
and then 0y01 to these bits.
2
C operation control
Address
Description
(0xF007_0000) + (0x000C)
TMPA901CM
2010-07-29