TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 606

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

AHB Bus
Original
Display
Data
(bypass)
3.18.2.3
Direct
AHB Slave
Example) If 0x00 pixel data is input in 8 bpp, the data is replaced into the lower 16-bit
into address as Replaced Display data is outputted. Moreover, if it is 16bpp, Original
Display Data is outputted as Replaced Display data)
lowest-order bit of pixel data is used to select either the higher 16 bits or lower 16 bits
of the palette RAM.
port RAM of 128 32 bits. Therefore, pixel data of two-pixel can be written in 1 word.
RAM Palette
Pallet address
A palette of 16 bits
Pixel data is replaced into data of in-palette 16 bits and then output.
(Original Display Data is processed as palette addresses, and then this data that
One word (32 bits) of palette RAM data equals to two pixels of data. Therefore, the
A palette structured with R:5 bits, G:5 bits, and B:5 bits is structured with a dual
I/F
0x0200
0x0204
0x0208
0x03FC
0x03F4
0x03F8
data for an address of 0xF420_0200.
If 0xFF pixel data is input in 8 bpp, the data is replaced into the higher 16-bit
data for an address of 0xF420_03FC.
31 30,29,28,27,26 ------------------------------------------------------------------------------ 04,03,02,01,00
I
I
I
I
I
I
I
I
B [4:0]
B [4:0]
B [4:0]
B [4:0]
B [4:0]
B [4:0]
B [4:0]
B [4:0]
Figure 3.18.2 Palette RAM
32bit Access
256 entries is incorporated.
TMPA901CM- 605
G [4:0]
G [4:0]
G [4:0]
G [4:0]
G [4:0]
G [4:0]
G [4:0]
G [4:0]
R [4:0]
R [4:0]
R [4:0]
R [4:0]
R [4:0]
R [4:0]
R [4:0]
R [4:0]
(128×32)
Pallet
I
I
I
I
I
I
I
I
B [4:0]
B [4:0]
B [4:0]
B [4:0]
B [4:0]
B [4:0]
B [4:0]
B [4:0]
G [4:0]
G [4:0]
G [4:0]
G [4:0]
G [4:0]
G [4:0]
G [4:0]
G [4:0]
R [4:0]
R [4:0]
R [4:0]
R [4:0]
R [4:0]
R [4:0]
R [4:0]
R [4:0]
One-pixel portion
TMPA901CM
2010-07-29
Replaced
Display
Data