TMPA901CMXBG Toshiba, TMPA901CMXBG Datasheet - Page 214

• Manufacturer Part Number: TMPA901CMXBG
• Description: Microcontrollers (MCU) 32-bit RISC MCU 16kb ARM926EJ 16kb 200Mhz
• Manufacturer: Toshiba

Specifications of TMPA901CMXBG

• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): -
• Rom Type: ROMless
• Ram (kbytes): 32
• Number Of Pins: 177
• Package: BGA
• Vcc: 3V
• Tft Lcd Controller: Y
• Touchscreen Controller: Y
• Usb Host Fs With Phy: Y
• Usb Device Hs With Phy: Y
• Sd Host Controller: -
• Cmos Image Sensor Interface: -
• I2s: 1
• Ssp (ch) Spi: 1
• I2mc/sio (ch): 1
• Uart/sio (ch): 2
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 8
• 10-bit Ad Converter: 4
• 12-bit Da Converter: -
• 16-bit Timer / Counter: 6
• Real Time Clock: Y
• Watchdog Timer: Y
• Osc Freq Detect: Y
• Low-power Modes: Y
• Lead Free Status / Rohs Status: Details

[31:16]
[15:13]
[12]
[11]
[10]
[9:7]
[6]
[5:3]
[2]
[1:0]
[Description]
Bit
a. < set_burst_align >
3.
operations, the settings values of this register will be updated to the configuration
register of the memory manager and enabled.
Memory burst boundary split setting:
0y000 = bursts can cross any address boundary
0y001 = split at the 32-beat burst boundary
0y010 = split at the 64-beat burst boundary
0y011 = split at the 128-beat burst boundary
0y100 = split at the 256-beat burst boundary
other = Reserved
This is a holding register for enabling setting values. By executing of the following
・The smc_direct_cmd Register takes place the UpdateRegs.
set_burst_align
set_bls
Reserved
-
set_wr_bl
set_wr_sync
set_rd_bl
set_rd_sync
set_mw
smc_set_opmode_3 (SMC Set Opmode Register)
Symbol
Bit
WO
WO
WO
WO
WO
WO
WO
WO
Type
TMPA901CM-213
Undefined
Undefined
Reset
Value
Read as undefined. Write as zero.
Memory burst boundary split setting:
(holding register)
0y000 = bursts can cross any address boundary
0y001 = split at the 32-beat burst boundary
0y010 = split at the 64-beat burst boundary
0y011 = split at the 128-beat burst boundary
0y100 = split at the 256-beat burst boundary
other = Reserved
Byte Enable (SMCBE0-3)bls timing setting:
0y0 = SMCCSn timing
0y1 = SMCWEn timing
Write as zero.
Read as undefined. Write as zero.
Write burst length
0y000 = 1 beat
0y001 = 4 beats
other = Reserved
Write synchronization mode setting
0y0 = asynchronous write mode
0y1 = Reserved
Read burst length
0y000 = 1 beat
0y001 = 4 beats
other = Reserved
Read synchronization mode setting:
0y0 = asynchronous read mode
0y1 = Reserved
Holding register of the memory data bus width set value:
0y00 = reserved
0y01 = 16 bits
0y10 = reserved
0y11 = Reserved
Address
Description
(0xF430_1000) + (0x0018)
TMPA901CM
2010-07-29